Fostering Design and Automation of
Electronic and Embedded Systems

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During Oct 2016, CEDA sponsored its first Design Automation Futures Workshop.  The goal was to bring prominent researchers in EDA to determine research directions in the area of neuromorphic computing.  Many experts from around the world presented designs/ideas/architectures developed for efficient/native execution of neural networks and cognitive algorithms. New devices such as memristors, RRAM and VRRRAM were also discussed.  Approximately 45 people attended the workshop. The presentations in each session were followed by panel discussions. The presentations and panel discussions were videotaped and are now available for viewing.  All slides can be viewed by accessing our Google folder here or by simply clicking the appropriate link in our shared Google Doc. This Google Doc contains the agenda with links to the presentations and videos.


 

The 2017 CAD Contest at ICCAD is a challenging, multi-month, research and development competition, focusing on advanced, real-world problems in the field of Electronic Design Automation. The contest is open to multi-person teams worldwide. Contestants can participate in one or more problems in the three areas of logic synthesis, global routing, and placement legalization. For more information, including registration details, detailed problem descriptions, and contest rules, please refer to the official contest website.

Read More CAD at ICCAD 2017 qr code

TCAD

The IEEE Council on Design Automation (CEDA) invites nominations for the position of Editor-in-Chief (EiC) for the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Self-nominations are permitted.

TCAD is a monthly published forum for papers in the area of electronic design automation and computer-aided design of integrated and embedded circuits and systems with analog, digital, mixed-signal, optical, or microwave components.

The term of duty of the new EiC begins on January 1, 2018, and ends December 31, 2019. The start of the period may be antedated if applicable. A period of approximately three months prior to the beginning of the term will be spent on enabling a smooth transition from the current EiC to the new EiC.

An EiC Selection Committee will evaluate all nominations and make recommendations to the CEDA Executive Committee for appointment based upon the CEDA bylaws. After the EiC is chosen, the Selection Committee will identify the Deputy EiC, in agreement with the newly appointed EiC. The EiC will then constitute an own Editorial Board of Associate Editors.

Nominations should be sent electronically to Jennifir McGillis (This email address is being protected from spambots. You need JavaScript enabled to view it.) and should be received by April 15, 2017, to ensure full consideration.

The nomination package should include:

  • Name, postal address, email address and telephone numbers of the nominee, and the publication (IEEE Trans. on CAD) for which the candidate is nominated.
  • Written confirmation that the candidate intends to accept a nomination for the EiC position and has the necessary resources to fulfill the position.
  • Curriculum vitae of the nominee, including the track record with IEEE service and publications details, with particular reference to TCAD.
  • Position statement of the nominee indicating the view of the candidate on the future of IEEE TCAD, the TCAD-specific opportunities and challenges, and any plans that the candidate wants to pursue.

The nominee must be a member in good standing of the IEEE. Desirable qualities of the candidates include an established track record of technical accomplishments, leadership, integrity and ethical standards, demonstrable organizational and management skills, and an energetic eagerness to continue moving the journal forward toward visibly higher levels of accomplishment and contributions to the relevant technical community.


 

IEEE CEDA is pleased to announce the nine individuals who came through the CEDA nomination process and have
been elevated to IEEE Fellow.

Class of 2017

w rhines
kchoi photo 0805
Walden C. Rhines
Mentor Graphics Corporation

 

for leadership and technology innovation in integrated circuit design and automation 
Kiyoung Choi
Seoul National University

for contribution to low-power, real-time, and reconfigurable systems
Xin Li Blue
WEIPING SHI 11
Xin Li
Duke University/Duke Kunshan Univ.

for contributions to modeling, analysis, and optimization of variability of integrated circuits
and systems
 
Weiping Shi
Texas A&M University

for contributions to modeling and design of VLSI interconnects
 
 Youngsoo Shin
 Valeria Bertacco 1352121919731
Youngsoo Shin
KAIST, Korea

for contributions to design tools for low 
power, high speed VLSI circuits and systems
Valeria Bertacco
University of Michigan

for contribution to computer-aided verification and reliable system design
 
Carloni Luca
Frank Liu
Luca Carloni
Columbia University
for contributions to system-on- chip design automation and latency-insensitive design
Frank Liu
IBM Research

for contributions to design for manufacturability of VLSI circuits

avladimirescu
 
Andrei Vladimirescu
BerkeleyWireless Research Center

for contributions to the development and 
commercial adoption of SPICE circuit simulation

WIE2017

IEEE WIE ILC 2017 is bringing together over 1500 women in STEM. Register today! Limited seating.

Attention: CEDA is offering conference travel awards for supporting three participants to attend the IEEE Women in Engineering International Leadership Conference (WIE-ILC), which is to take place on May 22-23, 2017 in San Jose, CA. The goal of this new award is to increase diversity in EDA and, in particular, help increase the number of women and minorities at leadership positions in academia and in industry in the EDA field. Details can be found here.

With the theme, LEAD BEYOND, the Women In Engineering (WIE) International Leadership Conference (ILC) 2017 will be held on 22-23 May 2017 in San Jose, California. From its inception in 2014, WIE ILC has grown to reach four times its initial audience. WIE ILC was key in advancing 2400 women in tech, connecting another 2000 virtually, providing 184 international travel grants and initiating 25+ new, technology product ideas. Learn more.

The conference will focus on entrepreneurship, empowerment, disruptive technology, innovation and leadership with exciting new tracks, contests and networking events. Be a part of this momentum - watch highlights from WIE ILC 2016. Partnership opportunities are also available. Volunteer opportunities and grants available exclusively for IEEE Women in Engineering members.

Join us at one of IEEE Women In Engineering’s largest events for leaders in STEM! Lead Beyond - Accelerating Innovative Women Who Change the World!


 

The CEDA sponsored Embedded Systems Letters will be included in the 'Clarivate Analytics' (formally Thomson Reuters IP and Science) Emerging Sources Citation Index. This is the first step in applying to the full Science Citation Index with Impact Factors. It represents a mark of quality and improves the visibility of a journal via the Web of Science. And it is good for authors, as ESL papers will now be included in their H-Index calculation.


 

Dr. Andrzej Strojwas, Keithley Professor of Electrical and Computer Engineering at Carnegie Mellon University, is the recipient of the 2016 Phil Kaufman Award. The award will be presented at a dinner honoring Dr. Strojwas on January 26, 2017, in San José, CA.

 

Andrjez Strojwas web

Dr. Stojwas has significantly advanced the art and science of IC design for manufacturability. Both academic and entrepreneur, Andrjez has excelled at both. Academically, he developed a number of CAD tools that addressed the statistical variations in the processing of integrated circuits and provided metrics to optimize the process and layouts to improve yield. He has also been an entrepreneur, bringing those metrics and methods to industry, where his techniques are used by nearly all advanced IC fabrication facilities. His efforts have helped the IC design and manufacturing industries cost effectively deliver the complex products we enjoy today.

Additional information on Dr. Strojwas' contributions is included in the full press release.

The ESD-Alliance and IEEE Council on EDA will honor Dr. Strojwas at an award presentation and dinner at 6:30 PM on January 26, 2017, at the 4th Street Summit in San José.


 

Message from the IEEE:

ORCID

All IEEE journals require an Open Researcher and Contributor ID (ORCID) for all authors.
ORCID is a persistent unique identifier for researchers and functions similarly to an article’s Digital Object Identifier (DOI). ORCIDs enable accurate attribution and improved discoverability of an author’s published work.

Read more: IEEE Message to Journal Authors

1. "Behavioral Simulation of Fractional-N Frequency Synthesizers and
Other PLL Circuits," by M.H. Perrott (vol. 19, no. 4, July/Aug. 2002,
pp. 74-83).

URL:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1018136

ABSTRACT:
Two techniques are presented that allow fast and accurate simulation of fractional-N synthesizers. A uniform time step allows implementation of these techniques in various simulation frameworks, such as Verilog, Matlab, and C or C++ programs. The techniques are also applicable to the simulation of other PLL systems, such as clock and data recovery circuits.


2. "AEthereal Network on Chip: Concepts, Architectures, and

Implementations," by K. Goossens, J. Dielissen, and A. Radulescu (vol.
22, no. 5, Sept./Oct. 2005, pp. 414-421).

URL:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1511973

ABSTRACT:
The continuous advances in semiconductor technology enable the
integration of increasing numbers of IP blocks in a single SoC.
Interconnect infrastructures, such as buses, switches, and networks on
chips (NoCs), combine the IPs into a working SoC. Moreover, the
industry expects platform-based SoC design to evolve to
communication-centric design, with NoCs as a central enabling
technology. In this article, we introduce the AEthereal NoC. The tenet
of the AEthereal NoC is that guaranteed services (GSs) - such as
uncorrupted, lossless, ordered data delivery; guaranteed throughput;
and bounded latency - are essential for the efficient construction of
robust SoCs. To exploit the NoC capacity unused by the GS traffic, we
provide best-effort services.


3. "High-Level Synthesis: Past, Present, and Future," by G. Martin and

G. Smith (vol. 26, no. 4, July/Aug. 2009, pp. 18-25).

URL:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5209959

ABSTRACT:
This article presents the history and evolution of HLS from research
to industry adoption. The authors offer insights on why earlier
attempts to gain industry adoption were not successful, why current
HLS tools are finally seeing adoption, and what to expect as HLS
evolves toward system-level design.


4. "A Survey of Hardware Trojan Taxonomy and Detection," by M.

Tehranipoor and F. Koushanfar (vol. 27, no. 1, Jan./Feb. 2010, pp.
10-25).

URL:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5406669

Editor's note:
Today's integrated circuits are vulnerable to hardware Trojans, which
are malicious alterations to the circuit, either during design or
fabrication. This article presents a classification of hardware
Trojans and a survey of published techniques for Trojan detection.


5. Demystifying 3D ICs: The Pros and Cons of Going Vertical," by W.R.

Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M.
Steer, and P.D. Franzon (vol. 22, no. 6, Nov./Dec. 2005, pp. 498-510).

URL:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1541910

ABSTRACT:
This article provides a practical introduction to the design
trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-μm technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-μm through-via
silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.


 2014/15 CEDA President Sani Nassif visited CEDA chapters in Pennsylvania, Beijing, Seoul, Shanghai, and Hong Kong in the fourth quarter of 2015. Each of the visits included meetings with chapter officers and members, and an introductory talk on the IEEE and CEDA (which can be found here.)

Each chapter will now make plans for 2016 activities which will be financially supported by CEDA and can include invited lectures (from the soon-to-be-announced CEDA Distinguished Lecturer program), local workshops and seminars, as well as membership development.

The goal of the visits as a whole was to energize the CEDA chapters and to encourage activity in 2016. Chapters are an important part of all IEEE societies, as they encourage and allow for local involvement with activities customized to each region. Chapters are particularly important in attracting participation from students, introducing them to the IEEE and to participation in professional societies in general. Chapters are also instrumental in reaching out to professionals who might be interested in career development and external visibility.

Watch for further news from our CEDA chapters in this space over the year!

BeijingorHongKong   Shanghai2 visit  

BeijingorHongKong2