Fostering Design and Automation of
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1. "Behavioral Simulation of Fractional-N Frequency Synthesizers and
Other PLL Circuits," by M.H. Perrott (vol. 19, no. 4, July/Aug. 2002,
pp. 74-83).


Two techniques are presented that allow fast and accurate simulation of fractional-N synthesizers. A uniform time step allows implementation of these techniques in various simulation frameworks, such as Verilog, Matlab, and C or C++ programs. The techniques are also applicable to the simulation of other PLL systems, such as clock and data recovery circuits.

2. "AEthereal Network on Chip: Concepts, Architectures, and

Implementations," by K. Goossens, J. Dielissen, and A. Radulescu (vol.
22, no. 5, Sept./Oct. 2005, pp. 414-421).


The continuous advances in semiconductor technology enable the
integration of increasing numbers of IP blocks in a single SoC.
Interconnect infrastructures, such as buses, switches, and networks on
chips (NoCs), combine the IPs into a working SoC. Moreover, the
industry expects platform-based SoC design to evolve to
communication-centric design, with NoCs as a central enabling
technology. In this article, we introduce the AEthereal NoC. The tenet
of the AEthereal NoC is that guaranteed services (GSs) - such as
uncorrupted, lossless, ordered data delivery; guaranteed throughput;
and bounded latency - are essential for the efficient construction of
robust SoCs. To exploit the NoC capacity unused by the GS traffic, we
provide best-effort services.

3. "High-Level Synthesis: Past, Present, and Future," by G. Martin and

G. Smith (vol. 26, no. 4, July/Aug. 2009, pp. 18-25).


This article presents the history and evolution of HLS from research
to industry adoption. The authors offer insights on why earlier
attempts to gain industry adoption were not successful, why current
HLS tools are finally seeing adoption, and what to expect as HLS
evolves toward system-level design.

4. "A Survey of Hardware Trojan Taxonomy and Detection," by M.

Tehranipoor and F. Koushanfar (vol. 27, no. 1, Jan./Feb. 2010, pp.


Editor's note:
Today's integrated circuits are vulnerable to hardware Trojans, which
are malicious alterations to the circuit, either during design or
fabrication. This article presents a classification of hardware
Trojans and a survey of published techniques for Trojan detection.

5. Demystifying 3D ICs: The Pros and Cons of Going Vertical," by W.R.

Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M.
Steer, and P.D. Franzon (vol. 22, no. 6, Nov./Dec. 2005, pp. 498-510).


This article provides a practical introduction to the design
trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-μm technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-μm through-via
silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.