1. "Behavioral Simulation of Fractional-N Frequency Synthesizers and
Other PLL Circuits," by M.H. Perrott (vol. 19, no. 4, July/Aug. 2002,
Two techniques are presented that allow fast and accurate simulation of fractional-N synthesizers. A uniform time step allows implementation of these techniques in various simulation frameworks, such as Verilog, Matlab, and C or C++ programs. The techniques are also applicable to the simulation of other PLL systems, such as clock and data recovery circuits.
2. "AEthereal Network on Chip: Concepts, Architectures, and
Implementations," by K. Goossens, J. Dielissen, and A. Radulescu (vol.
22, no. 5, Sept./Oct. 2005, pp. 414-421).
The continuous advances in semiconductor technology enable the
integration of increasing numbers of IP blocks in a single SoC.
Interconnect infrastructures, such as buses, switches, and networks on
chips (NoCs), combine the IPs into a working SoC. Moreover, the
industry expects platform-based SoC design to evolve to
communication-centric design, with NoCs as a central enabling
technology. In this article, we introduce the AEthereal NoC. The tenet
of the AEthereal NoC is that guaranteed services (GSs) - such as
uncorrupted, lossless, ordered data delivery; guaranteed throughput;
and bounded latency - are essential for the efficient construction of
robust SoCs. To exploit the NoC capacity unused by the GS traffic, we
provide best-effort services.
3. "High-Level Synthesis: Past, Present, and Future," by G. Martin and
G. Smith (vol. 26, no. 4, July/Aug. 2009, pp. 18-25).
This article presents the history and evolution of HLS from research
to industry adoption. The authors offer insights on why earlier
attempts to gain industry adoption were not successful, why current
HLS tools are finally seeing adoption, and what to expect as HLS
evolves toward system-level design.
4. "A Survey of Hardware Trojan Taxonomy and Detection," by M.
Tehranipoor and F. Koushanfar (vol. 27, no. 1, Jan./Feb. 2010, pp.
Today's integrated circuits are vulnerable to hardware Trojans, which
are malicious alterations to the circuit, either during design or
fabrication. This article presents a classification of hardware
Trojans and a survey of published techniques for Trojan detection.
5. Demystifying 3D ICs: The Pros and Cons of Going Vertical," by W.R.
Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M.
Steer, and P.D. Franzon (vol. 22, no. 6, Nov./Dec. 2005, pp. 498-510).
This article provides a practical introduction to the design
trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-μm technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-μm through-via
silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.
2014/15 CEDA President Sani Nassif visited CEDA chapters in Pennsylvania, Beijing, Seoul, Shanghai, and Hong Kong in the fourth quarter of 2015. Each of the visits included meetings with chapter officers and members, and an introductory talk on the IEEE and CEDA (which can be found here.)
Each chapter will now make plans for 2016 activities which will be financially supported by CEDA and can include invited lectures (from the soon-to-be-announced CEDA Distinguished Lecturer program), local workshops and seminars, as well as membership development.
The goal of the visits as a whole was to energize the CEDA chapters and to encourage activity in 2016. Chapters are an important part of all IEEE societies, as they encourage and allow for local involvement with activities customized to each region. Chapters are particularly important in attracting participation from students, introducing them to the IEEE and to participation in professional societies in general. Chapters are also instrumental in reaching out to professionals who might be interested in career development and external visibility.
Watch for further news from our CEDA chapters in this space over the year!
Kaufman Award Dinner and Celebration 2015
Photos from the event held in San Jose, California.
Additional photos can be found in our Facebook album (here).
The IEEE CEDA Board of Governors voted unanimously to approve the proposal to rename the IEEE CEDA Early Career Award to the "IEEE CEDA Ernest S. Kuh Early Career Award" in honor of the late Prof. Ernest S. Kuh, who made pioneering contributions in circuit theory, EDA, and engineering education.
The first Ernest S. Kuh Early Career Award will be presented to Prof. Zhiru Zhang, Cornell University, for outstanding contributions to algorithms, methodologies, and successful commercialization of high-level synthesis tools for FPGAs.
The award presentation will be conducted at the opening session of the International Conference On Computer-Aided Design (ICCAD)on November 2, 2015 at the DoubleTree Hotel in Austin, TX.
About Ernest S. Kuh
Ernest S. Kuh was a professor emeritus and dean of the UC Berkeley College of Engineering from 1973 to 1980. Professor Kuh passed away on June 27, 2015.
Ernest S. Kuh joined the Berkeley faculty in 1956 and made pioneering contributions in circuit theory, EDA of integrated circuits, and engineering education.
Ernest S. Kuh mentored and supervised several generations of graduate students who today occupy leadership positions in academia and industry.
Ernest S. Kuh was a Fellow of IEEE and AAAS. He received numerous awards and honors, including the ASEE Lamme Medal, IEEE Centennial Medal, IEEE Education Medal, IEEE Circuits and Systems Society Award, IEEE Millennium Medal, the 1996 C&C Prize, and the 1998 EDAC/IEEE CEDA Phil Kaufman Award.
Read More about Ernest S. Kuh (In Memoriam, to include a note from his son, Anthony Kuh)
Call-for-Nominations: CEDA Ernest S. Kuh Early Career Award (Due: April 15)
CEDA is calling for nominations for the Early Career Award in 2017.
The Award recognizes an individual who has made innovative and substantial
technical contributions to the area of Electronic Design Automation
in the early stages of her or his career.
This award will be presented at ICCAD. Full members of the IEEE at any
level (regular, senior, or fellow grades), whose highest educational degree
has been awarded no more than eight years prior to the date of the nomination
deadline, are eligible.
The award shall be based on contributions to the field of EDA.
Contribution will be measured based on technical merit and creativity
in performing research, and will be assessed based on the published record
of the individual and the references accompanying the nomination.
The award is intended to be equally available to contributors from academic
and industrial institutions.
Some of the specific criteria used will be the current and potential impact
of the individual's contributions, as well as contributions to the profession
The closing date for nominations: April 15.
The nomination can be made by anyone who is familiar with the individual's work.
The nominations are completed online using the CEDA nomination tool.
Before starting an online nomination, be sure to have the following information and supporting materials available:
- Name, affiliation, and contact information of nominating individual
- Nominee biographical information, including education and employment history
- Proposed citation (which IEEE CEDA may adjust)
- Three professional references/endorsements
- Include one or both of the following:
A selection of no more than three papers published by the nominee, with comments by the nominator limited to 100 words per paper.
A description of projects led by or contributed to by the nominee, with clear articulation of the role the nominee played and the relevant contributions.
Please refer to the following URL for more details.