Fostering Design and Automation of
Electronic and Embedded Systems

CEDA Newsletter Subscribe

Follow  facebook logo twitter button logo v2 by pixxiepaynee d5sog0x    Share  Affiliate with CEDA

Title: Embedded Deterministic Test

Dr. Janusz Rajski

From the Mentor Graphics Corporation, San Jose, CA


Design for testability (DFT) based on scan and automatic test pattern generation (ATPG) has been used for decades as a reliable methodology to generate high-quality patterns for manufacturing test. By the year 2000, the sizes of designs had grown so much that the volume of scan test data started causing a significant increase in test time, and required tester memory, consequently raising cost of test.

Embedded Deterministic Test (EDT) was developed to drastically reduce the volume of scan test data and test time. Typically when an ATPG tool targets multiple faults and creates a test cube, only a small percentage of scan cells gets specified. The remaining positions are usually filled with random values. As a result, the test patterns are grossly over-specified. EDT takes advantage of the low fill rate of test cubes to reduce the volume of test data and test time. It significantly increases the number of internal scan chains, reduces their length, and drives them by an on-chip decompressor implemented as a linear finite state machine. Moreover, it allows continuous flow decompression where the internal scan chains are loaded as the data is delivered to the decompressor. The compressed stimuli are computed by solving linear equations corresponding to internal scan cells with specified positions in partially specified test patterns. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, the EDT method results in compression ratios of 30 to 500 times.

To match the decompressor, a selective test response compactor is inserted between the internal scan chain outputs and the tester scan channel outputs. The compactor is controlled through the decompressor and is capable of handling a wide range of unknown (X) state profiles that result from false and multi-cycle paths as well as any other sources of X values. It can also operate in an over-drive mode, just like the decompressor, and provides very good diagnostic resolution.

On-chip test compression was commercially introduced only 5 years ago, and it has already become a mainstream DFT methodology. It is also one of the fastest adopted DFT technologies. The impact of a disruptive technology such as on-chip test compression goes far beyond the cost of manufacturing test. Test compression has changed the competitive landscape, opened up completely new opportunities in product quality and yield management, and has redefined DFT technology roadmaps. It stimulates research and development activities in new areas that until now were considered impractical, enables quality of testing that was unachievable until now, accelerates adoption of new fault models that take into account physical data bases and timing information, and changes how fault diagnosis and yield learning are done in a manufacturing environment.

Biographical sketch

Janusz Rajski is a Chief Scientist and Director of DFT Engineering at Mentor Graphics Corporation. He has published over 100 technical papers and holds seventeen US and international patents in the area of design for test. He is also the principal inventor of Embedded Deterministic Test (EDT™) technology and chief architect of the first commercial test compression product TestKompress™. Janusz received a number of awards including the 1993 Best Paper Award for a paper on logic synthesis published in IEEE Transactions on CAD, VTS 1995 and 1998 Best Paper Awards for papers on Embedded Test, and ITC 1999 and 2004 Honorable Mention Awards for papers on Logic BIST and Embedded Deterministic Test. In 2003 the President of Poland awarded the title of Professor of Sciences to Janusz for his fundamental contributions in the area of design and test of digital circuits and systems.

PlayPlay Video