Title: The Escalating Design Impact of Resolution-Challenged Lithography
For the first three decades of semiconductor scaling, the exponential increase in transistor density was largely driven by lithography resolution. Manufacturability and design efficiency were achieved through periodic increases in numerical aperture and reduction in exposure wavelength at a pace that kept the effective patterning complexity fairly constant node-to-node. This all changed almost exactly 30 years after Robert Dennard published his seminal paper describing MOSFET scaling rules in 1974. When the industry hit what most referred to as the 130nm technology node, existing 193nm wavelength lithography tools were rapidly running out of resolution with no real relief in sight until the massively disruptive introduction of extreme ultraviolet (EUV) lithography. What followed was more than a decade of technology nodes that ever more blatantly violated the fundamental laws of lithography resolution. The semiconductor industry was being kept alive by ‘Computational Scaling’, a series of increasingly complex resolution enhancement techniques (RET) with growing impact on design. This era of ‘sub-resolution scaling’ reached unprecedented levels of lithography-driven design impact with the introduction of double patterning in the 14nm technology node and continues to escalate as we extend 193nm optical lithography further past its physical limits.
This talk will briefly review the path leading up to the use of double patterning, elaborate on the challenges introduced by double patterning, and provide and overview of the solutions implemented to overcome these challenges. Unfortunately, the battle for resolution does not end there. The continued uncertainty surrounding the availability of EUV lithography for volume manufacturing forces the industry to eek out at least one more technology node with the existing lithography toolset. While the 14nm technology node pioneered the use of double patterning, the 10nm node ‘kicks it up a notch’ on the complexity scale. As will be shown, moving from double to triple patterning and introducing self-aligned double patterning through sidewall image transfer requires fundamental innovation in design rules, design methodologies, and design automation tooling.
The ultimate goal of this presentation is to communicate the sense of urgency with which we need to implement these innovative design solutions to maintain semiconductor scaling feasibility in this resolution challenged environment.
Lars Liebmann received BS and MS degrees in Nuclear Engineering and a PhD in Engineering Physics from Rensselaer Polytechnic Institute, Troy, NY. He joined IBM in 1991 where his work on lithography friendly designs for layout intensive Resolution Enhancement Techniques (RET) lead to his pioneering work on restricted design rules (RDR) as a practical means of preserving profitable CMOS scaling. His current technical focus in IBM’s Semiconductor Research and Development Center is design-technology co-optimization for sub-resolution patterning of leading-edge technology nodes. Dr. Liebmann holds over 60 patents, has published over 40 technical papers, and has received IBM’s Corporate and Outstanding Technical Achievement awards. For his work on lithography friendly design, Dr. Liebmann was appointed Distinguished Engineer of IBM and Fellow of SPIE - the International Society for Optical Engineering.