Title: Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization
Dr. Michael Orshansky
From the University of Texas at Austin, Austin, TX
Murai Mani, Ashish K. Singh, Michael Orshansky - Univ. of Texas, Austin, TX
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable parameters. The two levels of tuning operate within a single variability budget, and because their effectiveness depends on the magnitude and the spatial structure of variability their joint co-optimization is required. In this paper we develop a formal optimization algorithm for such co-optimization and link it to the control and measurement overhead via the formal notions of measurement and control complexity.
We describe an optimization strategy that unifies design-time gate-level sizing and post-silicon adaptation using adaptive body bias at the chip level. The statistical formulation utilizes adjustable robust linear programming to derive the optimal policy for assigning body bias once the uncertain variables, such as gate length and threshold voltage, are known. Computational tractability is achieved by restricting optimal body bias selection policy to be an affine function of uncertain variables. We demonstrate good run-time and show that 5-35% savings in leakage power across the benchmark circuits are possible. Dependence of results on measurement and control complexity is studied and points of diminishing returns for both metrics are identified.
Mike Orshansky is Assistant Professor in the Electrical and Computer Engineering Dept of the University of Texas at Austin. He received his undergraduate and PhD degrees from UC Berkeley. Prior to joining UT/Austin in 2003, he was a visiting Research Scientist at the Gigascale System Research Center and a Lecturer at UC Berkeley. He has also won an NSF CAREER Award and the Best Paper Award at DAC2005.
His research interests center on Design and CAD algorithms for manufacturability and yield improvement in the presence of process variability, in low-power circuit design, and in semiconductor device modelling.
The research he will describe today focuses on the problem of producing ICs which function correctly when manufacturing tolerances cannot be controlled accurately enough. It describes an optimization strategy which unifies design-time gate--level sizing and post-silicon adaptation using adaptive body bias at the chip level.