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Title: Parallel Transient Simulation on Multicore Shared-Memory Machines

Dr. Peng Li

From the ECE Department at Texas A&M University, TX, USA.

Authors

Wei Dong, Peng Li and Xiaoji Ye - Texas A&M University, CA

Abstract

While the emergence of multi-core shared-memory machines offers a promising computing solution to ever complex chip design problems, new parallel CAD methodologies must be developed to gain the full benefit of these increasingly parallel computing systems. We present a parallel transient simulation methodology and its multi-threaded implementation for general analog and digital ICs. Our new approach, Waveform Pipelining (abbreviated as WavePipe), exploits coarse grained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step by moving backwards in time, the latter performs predictive computing along the forward direction of the time axis. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardizing convergence and accuracy.

As a coarse-grained parallel approach, WavePipe not only requires low parallel programming effort, more importantly, it creates new avenues to fully utilize increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions.

Biographical sketch

Peng Li received his Ph.D. degree in electrical and computer engineering from Carnegie Mellon University in 2003. He has been an assistant professor at Texas A&M University since August 2004. His research interests include VLSI Design and CAD with an emphasis on analog/RF optimization and test, circuit simulation, parallel CAD algorithms, design and analysis of power and clock distribution networks, interconnect and timing analysis, statistical circuit analysis and optimization.

He received two Design Automation Conference (DAC) Best Paper Awards in 2003 and 2008, NSF Career Award in 2008, SRC Inventor Recognition Awards in 2001 and 2004, and a MARCO Inventor Recognition Award in 2006. He is an Associate Editor for IEEE Transactions on CAD and IEEE Transactions on Circuits and Systems II. He has served on the committees of a number of international conferences and workshops.

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