Fostering Design and Automation of
Electronic and Embedded Systems

CEDA Newsletter Subscribe

Follow  facebook logo twitter button logo v2 by pixxiepaynee d5sog0x    Share  Affiliate with CEDA

Title: Period Optimization for Hard Real-Time Distributed Automotive Systems

Ph.D. Candidate Qi Zhu

From the EECS Department at University of California, Berkeley, CA, USA.


Abhijit Davare, Qi Zhu, Marco Di Natale, Claudio Pinello, Sri Kanajan, Alberto Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA


The complexity and physical distribution of modern active-safety automotive applications requires the use of distributed architectures. These architectures consist of multiple electronic control units (ECUs) connected with standardized buses. When deploying the applications onto the distributed architectures, we need to decide the allocation of functional blocks to tasks and tasks to ECUs, the packing of signals to messages and the allocation of messages to buses, as well as the priorities, activation models and periods of tasks and messages.

In this work, we focus on the period assignment of tasks and messages in Controller Area Network (CAN) based systems. Given the allocation and priority assignment of tasks and messages, our approach automatically assigns periods for all tasks and messages in order to satisfy the end-to-end latency constraints in the system. Based on worst case analysis, the problem is formulated as mixed-integer geometric programming (MIGP). To efficiently solve the problem, MIGP is further approximated as a geometric programming (GP) formulation, and the approximation error between the two formulations is reduced with an iterative procedure.

Biographical sketch

Qi Zhu is a Ph.D. candidate in Electrical Engineering and Computer Sciences at University of California, Berkeley. Qi obtained a B.E. in Computer Sciences from Tsinghua University in 2003. He earned a Master's degree in EECS from University of California, Berkeley in 2006. His research interests are in the areas of system level design and synthesis, logic synthesis and embedded system design.