Title: IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors
Dr. Subhasish Mitra
From the Dept. of EECS, Stanford University, USA.
Sung-Boem Park, Subhasish Mitra, Stanford University, Palo Alto, CA, USA
IFRA, an acronym for Instruction Footprint Recording and Analysis, overcomes major challenges associated with a very expensive step in post-silicon validation of processors - pinpointing the bug location and the instruction sequence that exposes the bug (also called exposing stimulus) from a system failure such as a crash. Major benefits of IFRA over traditional techniques for post-silicon bug localization are: 1. It does not require full system-level reproduction of bugs, and, 2. It does not require full system-level simulation. Hence, it can overcome major hurdles that limit the scalability of traditional post-silicon validation methodologies. Results on a complex super-scalar processor demonstrate that IFRA is effective in accurately localizing electrical bugs with very little impact on overall chip area.
Subhasish Mitra is an Assistant Professor in the Departments of Electrical Engineering and Computer Science of Stanford University where he leads the Stanford Robust Systems Group. His research interests include: 1. Robust system design; 2. VLSI design, CAD, validation and test; and 3. Design for emerging nanotechnologies. Prior to joining Stanford, Prof. Mitra was a Principal Engineer at Intel Corporation.
Prof. Mitra has co-authored 100+ technical papers, and has invented design and test techniques that have seen wide-spread proliferation in the semiconductor industry. His X-Compact technique for test compression is used by 50+ Intel products, and is supported by major CAD tools. His work on imperfection-immune circuits using carbon nanotubes, jointly with his students and collaborators, has been highlighted by the MIT Technology Review, Semiconductor Research Corporation, EE Times, and several others.
Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers (PECASE, the highest honor bestowed by the US government on early career outstanding scientists and engineers), National Science Foundation CAREER Award, Terman Fellowship, IEEE CAS/CEDA Pederson Award for the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM SIGDA Outstanding New Faculty Award, Best Paper Award at the IEEE/ACM Design Automation Conference, a Divisional Recognition Award from Intel "for a Breakthrough Soft Error Protection Technology," a Best Paper Award at the Intel Design and Test Technology Conference for his work on Built-In Soft Error Resilience, and the Intel Achievement Award, Intel's highest corporate honor, "for a breakthrough test compression technology."