Special Session on Future Electronic Design Automation (EDA): Next Generation Design Automation for Accelerating the Reboot

Nov 8 2017

Special Session on Future Electronic Design Automation (EDA): Next Generation Design Automation for Accelerating the Reboot


November 8, Wednesday, 2-4pm.

Shishpal Rawat (President of the IEEE Council on EDA)
Ayse K. Coskun (Associate Professor at Boston University and IEEE Initiatives Liaison of the IEEE CEDA)

Future computing systems will integrate a collection of new devices, architectures, or brand new computing paradigms. To enable rapid innovation along these new axes and to ensure that design quality and performance are not left on the table, new methods and tools for designing and optimizing these emerging systems are becoming essential. Electronic design automation (EDA) tools have provided the silicon industry with the ability to innovate and scale at an unprecedented pace over the past few decades. Now it is an exciting time to create the new generation EDA approaches to address the challenges of emerging computing systems. This special session discusses the EDA challenges and approaches in several emerging computing fields, including in specification, design, verification, and assembly of hybrid architectures, approximate computing systems, and synthetic biological systems.


Yu (Kevin) Cao, Arizona State University

Douglas Densmore, Boston University

Arijit Raychowdhury, Georgia Institute of Technology

Shobha Vasudevan, University of Illinois at Urbana-Champaign


2:00 pm   Welcome and Overview, Prof. Ayse Coskun

2:10 pm “EDA Challenges in Designing Computing Systems with post-CMOS Devices”, Prof. Arijit Raychowdhury

As computing paradigms expand to include non-Boolean/non-symbolic computing models, neuro-inspired hardware and dynamical and stochastic systems, efficient tools and design methodologies need to be developed to cater to these design trends. Much of this growth in alternative designs and architectures is fueled by emerging applications on one hand and post-CMOS device technologies on the other. This brings significant challenges to both technology CAD and system simulation. As we try to harness unique device and material properties at higher levels of system design, cross-layer design and verification need to happen often breaking traditional models of abstraction. This talk will discuss some of the trends in post-CMOS devices, challenges in modeling computing systems with these devices and how EDA tools need to evolve to address these challenges. In particular, spin-based systems and oxide electronics will be used as prototypical examples of platform technologies for realizing neuromorphic hardware and dynamical systems that can solve complex computational tasks.

About the Speaker: Arijit Raychowdhury is currently an Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology where he holds the ON Semiconductor Chair Professorship. His industry experience includes five years as a Staff Scientist in the Circuits Research Lab, Intel Corporation, and a year as an Analog Circuit Designer with Texas Instruments Inc. His research interests include low power digital and mixed-signal circuit design, and exploring interactions of circuits with device technologies. Dr. Raychowdhury holds more than 25 U.S. and international patents and has published over 100 articles in journals and refereed conferences. He and his students have received several best paper awards and fellowships.

2:35 pm “Verification in the nanoscale era of computing”, Prof. Shobha Vasudevan

We live in interesting times. Our systems have unprecedented levels of device integration. Analog and mixed-signal components and devices form increasingly large parts of our designs built for low power and high flexibility. New architectures and models of computation that embrace variation like neuromorphic and stochastic computing are a part of our horizon. Architectures specialized for neural networks and learning algorithms are being built as massive undertakings in contemporary industry as well as with hardware accelerators. Application specific hardware has seen a healthy resurgence for machine learning and vision applications.

With all these innovations in architecture and design, how do we know if we are getting them right? As designs get more complicated, the “price of the lunch” is paid by verification complexity. We have always aspired to build systems we don’t know to check. This problem is going to get much more challenging for systems of the future. What does it mean to verify these massively integrated systems, with new features, new models of computation, non-traditional architectures, and new applications? How do we characterize, define, execute and sign off on the correctness of the most complex systems known to humans? This talk touches upon these questions and attempts to answer some of them.

About the Speaker: Shobha Vasudevan is an associate professor in the departments of Electrical and Computer Engineering and Computer Science at the University of Illinois at Urbana-Champaign. Her research interests span hardware systems and algorithms. In hardware- verification, analog/mixed-signal verification, and post Silicon validation; in algorithms- non-convex and functional optimization, graph search, feature engineering and their applications to data analysis. She has won several best paper awards including one at DAC 2014, ACM SIGDA Outstanding New Faculty Award, IEEE early career award, IBM faculty award, Dean's award for research excellence in UIUC, YMCA award for service to women in engineering. GoldMine, a verification software from her group has been developed into a commercial product since 2014 and licensed by multiple companies from UIUC.

3:00 pm “Accurate Learning On-a-chip with Inaccurate Devices: A Hybrid Approach with Random Sparse Adaptation”, Prof. Yu (Kevin) Cao

Hardware acceleration of machine learning algorithms promises high performance, energy efficiency, and a small footprint. The platform can be CMOS based, either analog or digital, or the integration of post-CMOS devices, such as the resistive cross-point array. As device size scales, these platforms inevitably face excessive variations and other non-ideal effects, leading to reduced precision in weight storage and significant degradation in learning accuracy. This talk discusses a fundamentally novel approach to overcome this issue: instead of calibrating the precision at the device level, we exploit the inherent adaptation of the training step to guarantee accuracy at the system level. This approach integrates a small, high-precision SRAM array with the main, low-precision weight array, and only performs random sparse adaptation (RSA) on SRAM to compensate the accuracy loss. As demonstrated in the RRAM design, RSA achieves high accuracy even under severe variations and is 10-100X faster than conventional device-level calibration.

About the Speaker: Yu Cao received the B.S. degree in physics from Peking University in 1996. He received the M.A. degree in biophysics and the Ph.D. degree in electrical engineering from University of California, Berkeley, in 1999 and 2002, respectively. He is now a Professor of Electrical Engineering at Arizona State University. He has published numerous articles and two books on nano-CMOS modeling and physical design. His research interests include physical modeling of nanoscale technologies, design solutions for variability and reliability, reliable integration of post-silicon technologies, and hardware design for on-chip learning. He is a Fellow of the IEEE.

3:25 pm “How Bio-Design Automation Can Help Reboot Computing: Lessons, Challenges, and Future Directions”, Prof. Douglas Densmore

Advances in electronic design automation (EDA) have been crucial in the development of complex electronic systems. The ability to independently specify, design, and assemble electronic systems at various abstraction levels has enabled tremendous growth in the semiconductor industry. In addition to growth, EDA has introduced ways to reduce design errors, increase performance, and deliver new products at an increased pace. As the field of synthetic biology grows, it is going to be vital to begin to look at introducing design methodologies that also enable specification, design, and physical assembly. This talk will introduce my vision for creating tools to address these issues which take techniques from EDA and apply them where appropriate to bio-design automation (BDA). I will discuss how to leverage traditional logic synthesis techniques to create genetic circuits for synthetic biology using a tool called “Cello”.

About the Speaker: Douglas Densmore is an Associate Professor of Electrical and Computer Engineering at Boston University. He creates electronic design automation inspired software tools for synthetic biology. He is a founding member of the BU Biological Design Center (BDC), head of the NSF’s “Living Computing Project” and a Senior Member of the IEEE and ACM.

3:50 pm Q&A and Final Thoughts

See Complete ICRC Schedule


Wed, Nov 8th, 2017 to Wed, Nov 8th, 2017



Washington, DC