2015 CAD Contest at ICCAD
Contest chair: Natarajan Viswanathan
Contest co-chairs: Shih-Hsu Huang, Rung-Bin Lin, and Myung-Chul Kim
The CAD contest at ICCAD is among the premier research and development contests in the field of Electronic Design Automation (EDA). Since its inaugural year of 2012, the CAD contest at ICCAD has been a worldwide competition, conducted with joint sponsorship from IEEE CEDA and the Ministry of Education, Taiwan. Over the years, the contest has presented challenging problems in varied topic areas, such as logic synthesis, physical design, design for manufacturability, and 3D IC design. Together with the associated real-world benchmarks and common evaluation frameworks, the contest problems have played a key role in advancing the state-of-the-art in EDA. Additionally, they have fostered productive industry-academia collaboration. In the past three years, the contest has witnessed a progressive increase in worldwide participation: 56 teams from 7 countries/regions in 2012, 87 teams from 9 countries/regions in 2013, and 93 teams from 9 countries/regions in 2014. Thus far, it has lead to more than 35 publications in top-tier conferences and journals, which have undoubtedly boosted EDA research and extended the impact of the contest.
Continuing this rich tradition, the 2015 CAD Contest at ICCAD attracted 112 multi-person teams from 12 countries/regions, including Taiwan, Mainland China, Hong Kong, Korea, India, Iran, USA, Brazil, Belgium, Sweden, Russian Federation, and Egypt. In total, these teams comprised of 247 students and 60 professors. Contestants participated in one or more problems in the three topic areas of (a) system-level design, (b) logic synthesis and verification, and (c) physical design. Along with the release of the contest benchmarks, the contest results were announced at ICCAD 2015, held from November 2-6 in Austin, Texas. The contest problems and final results are summarized as follows.
The first topic, chaired by Arvind Sridhar (IBM Research - Zurich, Switzerland), Mohamed M. Sabry (Stanford University, USA) and David Atienza (ESL-EPFL, Switzerland), addressed the problem of 3D Interlayer Cooling Optimized Network (3D-ICON). Interlayer single-phase liquid cooling is an effective cooling mechanism for the high-heat dissipated in high-performance 3D-stacked processing architectures. The contestants were required to find an optimized cooling network that minimized a specific cost function subject to design and physical constraints. First place went to a team from The Chinese University of Hong Kong (Hong Kong) led by Professor Evangeline F.Y. Young and Professor Bei Yu (students: Jian Kuang, Gengjie Chen, Zhiliang Zeng, Hang Zhang). Second place went to a team from National Tsing Hua University (Taiwan) headed by Professor Shih-Chieh Chang. Third place went to Fudan University (Mainland China) directed by Professor Heng-Liang Zhu and Professor Xuan Zeng.
The second topic, chaired by Jacky Chih-Jen Hsu (Cadence Design Systems Inc., Taiwan) addressed the problem of large-scale equivalence checking and function correction. Efficient equivalence checking and functional correction on large-scale logic designs are crucial technologies for handling today’s demanding design cycles. The contestants were expected to insert the corresponding cuts to isolate the function, whilst minimizing the cost. The first place went to a team from Lomonosov Moscow State University (Russia) led by Professor Mikhail Shupletsov (students: Grigorii Antiufeev, Evgeny Zenin, Vladimir Zhukov). The second place went to a team from National Taiwan University (Taiwan) headed by Professor Chung-Yang (Ric) Huang. Third place went to a team from National Taiwan University (Taiwan) directed by Professor Jie-Hong Roland Jiang.
The third topic, chaired by Myung-Chul Kim (IBM Corporation, USA) and Jin Hu (IBM Corporation, USA), addressed the problem of incremental timing-driven placement. The objective of timing-driven placement is to optimize locations of circuit elements to reduce the interconnect delay for timing critical paths, which is becoming a major limiting factor for timing closure in nanometer-scale VLSI designs. For each benchmark design, the evaluation metric considered both the quality of the placement solution and runtime. First place went to a team from Federal University of Santa Catarina (Brazil) led by Professor José Luís Güntzel and Professor Luiz C. V. dos Santos (students: Vinicius Livramento, Chrystian Guth, Renan Netto). Second place went to a team from the Federal University of Rio Grande do Sul (Brazil) headed by Professor Marcelo Johann and Professor Ricardo Reis. Third place went to a team from The Chinese University of Hong Kong (Hong Kong) directed by Professor Evangeline F.Y. Young.
The problems, associated benchmark suites, and final results are available at the official contest website: http://cad-contest.el.cycu.edu.tw/CAD-contest-at-ICCAD2015/index.html. Please keep your eyes open for publications that are driven by the 2015 CAD contest in upcoming conferences and journal editions.
The call-for-participation for 2016 CAD Contest at ICCAD is underway. The details have been announced on the contest website. You are invited to participate!
Photos from the event: