Fostering Design and Automation of
Electronic and Embedded Systems

 

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  • Design & Test welcomes several new members to its editorial board, effective Jan. 1st 2016!

LATEST NEWSLETTER & ISSUE

 

Design & Test
Magazine
Volume 34, Issue 3 (May/June)

CEDA: IEEE Council on Electronic Design Automation

CAS: Circuits & Systems Society

TTTC: Test Technology Technical Council

SSCS: IEEE Solid-State Circuits Society

IEEE

 


Highlights

Special Issue on "Critical and Enabling Techniques for Emerging Memories"

 

Survey on "Recent Technology Advances of Emerging Memories"

Perspective by Krishnendu Chakrabarty, "Quo Vadis Test? The Past, the Present, and the Future: No Longer a Necessary Evil"

Roundtable by David Yeh on "Designing Secure Electronics: Challenges From a Hardware Perspective" (Free Access)

 

Book Review by Scott Davidson "Cyber–Physical System Design With Sensor Networking Technologies"

 

May/June 2017 Content


From the EIC

Emerging Memory Technologies

 

View full article (PDF) here.


Critical and Enabling Techniques for Emerging Memories

Guest Editors' Introduction: Critical and Enabling Techniques for Emerging Memories

 

View full article (PDF) here.

Recent Technology Advances of Emerging Memories

 

Phase change memory, spin-transfer torque random access memory, and resistive random access memory are three major emerging memory technologies that ... read more.

View full article (PDF) here.

Correlated Effects on Forming and Retention of Al Doping in HfO2-Based RRAM

 

Retention time is one of the key parameters of emerging memories, which define the time duration the data can be retained when the power supply is removed. In this work, the authors investigate... read more.

View full article (PDF) here.

Reliable Nonvolatile Memories: Techniques and Measures

 

Reliability continues to be a severe challenge in the development of emerging memories. In this article, the authors... read more.

View full article (PDF) here.

Multisource Indoor Energy Harvesting for Nonvolatile Processors

 

One promising application of emerging memories is to implement a nonvolatile memory hierarchy that can retain the data when power is removed. In this work, the authors... read more.

View full article (PDF) here.


General Interest Papers

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

 

To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging technologies. In this article, ... read more.

View full article (PDF) here.

Interdependencies of Degradation Effects and Their Impact on Computing

 

Process variations, aging and wearout, are nonidealities that lead to suboptimal system performance and increased power. In order to understand the effects... read more.

View full article (PDF) here.


Departments

Post-Silicon Validation in the SoC Era: A Tutorial Introduction

 

Access Article (PDF) here.

Quo Vadis Test? The Past, the Present, and the Future: No Longer a Necessary Evil

 

Access Article (PDF) here.

Designing Secure Electronics: Challenges From a Hardware Perspective

 

Free Access Article (PDF) here.

Recap of the 22nd Asia and South- Pacific Design Automation Conference

 

Access Article (PDF) here.

Cyber-Physical System Design With Sensor Networking Technologies

 

Free Access Article (PDF) here.

Being Connected

 

Free Access Article (PDF) here.


Click for Table-of-Contents.


Jörg Henkel, KIT, Karlsruhe
Editor-in-Chief

 

Current Issue Details (Vol. 34, Issue 2)

 

Table of Contents

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