To recognize the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Historical Background: The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award is sponsored by the IEEE Council on EDA and recognizes the best paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems publication. The award is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research. Anyone who is an author of a paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award is eligible for nomination. Prize: $500 for each author (maximum of $2,000 per award) and Certificate plaque Funding: Funded by the IEEE Council on Electronic Design Automation. Presentation: Presented annually at DAC. Basis for Judgement: General quality, originality, contributions, subject matter, and timeliness. Eligibility: Authors of papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award. Nomination Details: Nomination deadline is 28 February of the award year. Sorry...This form is closed to new submissions. Award Recipients 2008 Alan Mishchenko, Jin S. Zhang, Subarna Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske 2008 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Using simulation and satisfiability to compute flexibilities in Boolean networks IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 743-755, May 2006. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624509 2007 Guoyong Shi, Bo Hu, C.-J. Richard Shi 2007 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × On Symbolic Model Order Reduction IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1257-1272, July 2007. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1634623&isnumber=34277 2006 Mark Kassab, Janusz Rajski, Jerzy Tyszer, Nilanjan Mukherjee 2006 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Embedded Deterministic Test IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 23, no. 5, pp. 776-792, May 2006. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1291587&isnumber=28765 2005 Subhasish Mitra, Kee Sup-Kim 2005 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × X-compact: An Efficient Response Compaction Technique IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, pp. 421-432 March 2004. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624509 2004 Vivek V. Shende, Aditya K. Prasad, Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes - Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award, John P. Hayes 2004 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Synthesis of Reversible Logic Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710-722, June 2003. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1201583 2003 Yirng-An Chen, Randal E. Bryant 2003 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × An Efficient Graph Representation for Arithmetic Circuit Verification IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp. 1443-1454, December 2001. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=969437 2002 Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura 2002 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Floorplanning Using a Tree Representation 2001 Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya 2001 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × SPFD: A New Method to Express Functional Flexibility IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 840-849, August 2000. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=856972 2000 Chris Chu, Martin D.F.Wong 2000 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × A Quadratic Programming Approach to Simultaneous Buffer Insertion/Sizing and Wire Sizing IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 787-798, June 1999. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=766728 1999 Altan Odabasioglu, Mustafa Celik, Larry Pileggi 1999 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, pp. 645-654, August 1998. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=712097&url=http%3A//ieeex… Pagination « « First ‹ ‹‹ 1 2
Using simulation and satisfiability to compute flexibilities in Boolean networks IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 743-755, May 2006. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624509
On Symbolic Model Order Reduction IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1257-1272, July 2007. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1634623&isnumber=34277
Embedded Deterministic Test IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 23, no. 5, pp. 776-792, May 2006. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1291587&isnumber=28765
X-compact: An Efficient Response Compaction Technique IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, pp. 421-432 March 2004. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624509
Synthesis of Reversible Logic Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710-722, June 2003. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1201583
An Efficient Graph Representation for Arithmetic Circuit Verification IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp. 1443-1454, December 2001. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=969437
SPFD: A New Method to Express Functional Flexibility IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 840-849, August 2000. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=856972
A Quadratic Programming Approach to Simultaneous Buffer Insertion/Sizing and Wire Sizing IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 787-798, June 1999. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=766728
PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, pp. 645-654, August 1998. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=712097&url=http%3A//ieeex…
