IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award

To recognize the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Historical Background:

The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award is sponsored by the IEEE Council on EDA and recognizes the best paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems publication.

The award is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research. Anyone who is an author of a paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award is eligible for nomination.

Prize:

$500 for each author (maximum of $2,000 per award) and certificate

Funding:

Funded by the IEEE Council on Electronic Design Automation.

Presentation:

The award will be presented at the ICCAD conference.

Basis for Judging:

General quality, originality, contributions, subject matter, and timeliness.

Eligibility:

Authors of papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award. Self Nominations are permitted. Each nominator may only nominate one paper only.

Nomination Details:

Nomination deadline is 28 February of the award year.

Nomination Form:

Nominate for this Award

Recipients

2014

"Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, Issue 10, pp. 1533 - 1545, September 2013

Zheng Zhang

, Tarek A. El-Moselhy, Ibrahim M. Elfadel, and Luca Daniel

2013

"Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Issue 12, pp. 1814 - 1827, December 2011

Wangyang Zhang, Xin Li

Xin Li

3 (Southeastern U.S.)

Biography

Prof. Xin Li received the Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, Pennsylvania, in 2005, and the M.S. and B.S. degrees in Electronics Engineering from Fudan University, Shanghai, China, in 2001 and 1998, respectively.

In 2005, he co-founded Xigmix Inc. to commercialize his PhD research, and served as the Chief Technical Officer until the company was acquired by Extreme DA in 2007. In 2011, Extreme DA was further acquired by Synopsis (Nasdaq: SNPS). From 2009 to 2012, he was the Assistant Director for FCRP Focus Research Center for Circuit & System Solutions (C2S2), a national consortium of 13 research universities (CMU, MIT, Stanford, Berkeley, UIUC, UMich, Columbia, UCLA, among others) chartered by the U.S. semiconductor industry and U.S. Department of Defense to work on next-generation integrated circuit design challenges. From 2014 to 2015, he was the Assistant Director for the Center for Silicon System Implementation (CSSI), a CMU research center with 20 faculty members working on integrated circuits and systems. His research interests include integrated circuit, signal processing and data analytics.

He was an Associate Editor of IEEE Trans. on Biomedical Engineering (TBME), IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), ACM Trans. on Design Automation of Electronic Systems (TODAES), IEEE Design & Test (D&T), and Journal of Low Power Electronics (JOLPE). He was the Guest Editor for IEEE TCAD, IEEE TNANO, IEEE TBD, IEEE D&T, IEEE JETCAS, ACM TCPS, ACM JETC and VLSI Integration. He served on the Executive Committee of ACM Special Interest Group on Design Automation (SIGDA), IEEE Systems, Man, and Cybernetics Society Technical Committee on Cybernetics for Cyber-Physical Systems (TCCCPS), and IEEE Computer Society Technical Committee on VLSI (TCVLSI). He was the General Chair of ISVLSI, iNIS and FAC, and the Technical Program Chair of CAD/Graphics. He also served on the ACM/SIGDA Outstanding PhD Dissertation Award Selection Committee, the IEEE TTTC E. J. McCluskey Best Doctoral Thesis Selection Committee, the IEEE Outstanding Young Author Award Selection Committee, the Executive Committee of ISVLSI, GLSVLSI and iNIS, and the Technical Program Committee of DAC, ICCAD, ITC, ISVLSI, FAC, CAD/Graphics, ASICON and VLSI. He received the NSF Faculty Early Career Development Award (CAREER) in 2012, two IEEE Donald O. Pederson Best Paper Awards in 2013 and 2016, the Best Paper Award from Design Automation Conference (DAC) in 2010, two IEEE/ACM William J. McCalla ICCAD Best Paper Awards in 2004 and 2011, and the Best Paper Award from International Symposium on Integrated Circuits (ISIC) in 2014. In addition to these awards, he also received six Best Paper Nominations from Design Automation Conference (DAC), International Conference on Computer-Aided Design (ICCAD) and Custom Integrated Circuits Conference (CICC).

Affiliation(s)

Duke University

United States

, Frank Liu, Emrah Acar, and Ronald D. (Shawn) Blanton

2012

"An Analytical Approach for Network-on-Chip Performance Analysis"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, Issue 12, pp. 2001-2013, December 2010

Umit Ogras

, Paul Bogdan

, and Radu Marculescu

2011

"Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, Issue 8, pp. 1176-1189, August 2009

Amith Singhee

2010

"FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 1, pp. 70-83, January 2008

Chris Chu, and Yiu-Chung Wong

2009

"Systematic and Automated Multiprocessor System Design, Programming, and Implementation"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 3, pp. 542-555, March 2008

Hristo Nikolov, Todor Stefanov, and Ed F. Deprettere

2008

"Using Simulation and Satisfiability to Compute Flexibilities in Boolean Networks"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 5, pp. 743-755, May 2006

Alan Mishchenko, Jin S. Zhang, Subarna Sinha, Jerry R. Burch, Robert K. Brayton, and Malgorzata Chrzanowska-Jeske

2007

"On Symbolic Model Order Reduction"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 7, pp. 1257-1272, July 2007

Guoyong Shi, Bo Hu, and C.-J. Richard Shi

2006

"Embedded Deterministic Test"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 5, pp. 776-792, May 2006

Mark Kassab, Janusz Rajski, Jerzy Tyszer, and Nilanjan Mukherjee

2005

"X-compact: An Efficient Response Compaction Technique"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 3, pp. 421-432, March 2004

Subhasish Mitra

6 (Western U.S.)

Biography

Subhasish Mitra is currently a Professor of Electrical Engineering and Computer Science at Stanford University, Stanford, CA, USA, where he directs the Stanford Robust Systems Group and co-leads the computation focus area of the Stanford SystemX Alliance. He is also a Faculty Member with the Neurosciences Institute, Stanford University. He holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI, Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation, Santa Clara, CA, USA. His current research interests include broadly across robust computing, nanosystems, VLSI design, validation, test, and electronic design automation, and neurosciences. He along with his students and collaborators demonstrated the first carbon nanotube computer and the first 3-D nanosystem with computation immersed in data storage. These demonstrations received widespread recognitions (cover of Nature, Research Highlight to the U.S. Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, The Economist, Electronic Engineering Times, IEEE Spectrum, MIT Technology Review, National Public Radio, The New York Times, Scientific American, Time, The Wall Street Journal, The Washington Post, and numerous others worldwide). His earlier work on X-Compact test compression has been a key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial electronic design automation tools. He is a Fellow of the Association for Computing Machinery (ACM) and IEEE. He received the Association for Computing Machinery Special Interest Group on Design Automation/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test-of-time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel's highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He along with his students published several award-winning papers at major venues, including the ACM/IEEE Design Automation Conference, the IEEE International Solid-State Circuits Conference, the ACM/IEEE International Conference on Computer-Aided Design, the IEEE International Test Conference, the IEEE Transactions on Computer-Aided Design, the IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. He was honored several times by graduating seniors for being important to them during their time at Stanford. He has served on the Defense Advanced Research Projects Agency's Information Science and Technology Board as an Invited Member.

Affiliation(s)

Stanford University

United States

, and Kee Sup-Kim

Recipients

2014

"Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos"

2013

"Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits"

2012

"An Analytical Approach for Network-on-Chip Performance Analysis"

2011

"Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design"

2010

"FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design"

2009

"Systematic and Automated Multiprocessor System Design, Programming, and Implementation"

2008

"Using Simulation and Satisfiability to Compute Flexibilities in Boolean Networks"

2007

"On Symbolic Model Order Reduction"

2006

"Embedded Deterministic Test"

2005

"X-compact: An Efficient Response Compaction Technique"

Questions about IEEE CEDA?

Stay connected with IEEE CEDA Currents