To recognize the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Historical Background: The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award is sponsored by the IEEE Council on EDA and recognizes the best paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems publication. The award is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research. Anyone who is an author of a paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award is eligible for nomination. Prize: $500 for each author (maximum of $2,000 per award) and certificate Funding: Funded by the IEEE Council on Electronic Design Automation. Presentation: The award will be presented at the ICCAD conference. Basis for Judging: General quality, originality, contributions, subject matter, and timeliness. Eligibility: Authors of papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award. Self Nominations are permitted. Each nominator may only nominate one paper only. Nomination Details: The nomination deadline is 28 February of the award year. Nomination Form: Nominate for this Award Recipients 2015 "Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, Issue 10, pp. 1463 - 1475, October 2014 Kai Hu, Feiqiao Yu, Tsung-Yi Ho, and Krishnendu Chakrabarty Acceptance Speech × 2014 "Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, Issue 10, pp. 1533 - 1545, September 2013 Zheng Zhang, Tarek A. El-Moselhy, Ibrahim M. Elfadel, and Luca Daniel Acceptance Speech × 2013 "Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Issue 12, pp. 1814 - 1827, December 2011 Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, and Ronald D. (Shawn) Blanton Acceptance Speech × 2012 "An Analytical Approach for Network-on-Chip Performance Analysis" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, Issue 12, pp. 2001-2013, December 2010 Umit Ogras, Paul Bogdan, and Radu Marculescu Acceptance Speech × 2011 "Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, Issue 8, pp. 1176-1189, August 2009 Amith Singhee Acceptance Speech × 2010 "FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 1, pp. 70-83, January 2008 Chris Chu, and Yiu-Chung Wong Acceptance Speech × 2009 "Systematic and Automated Multiprocessor System Design, Programming, and Implementation" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 3, pp. 542-555, March 2008 Hristo Nikolov, Todor Stefanov, and Ed F. Deprettere Acceptance Speech × 2008 "Using Simulation and Satisfiability to Compute Flexibilities in Boolean Networks" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 5, pp. 743-755, May 2006 Alan Mishchenko, Jin S. Zhang, Subarna Sinha, Jerry R. Burch, Robert K. Brayton, and Malgorzata Chrzanowska-Jeske Acceptance Speech × 2007 "On Symbolic Model Order Reduction" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 7, pp. 1257-1272, July 2007 Guoyong Shi, Bo Hu, and C.-J. Richard Shi Acceptance Speech × 2006 "Embedded Deterministic Test" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 5, pp. 776-792, May 2006 Mark Kassab, Janusz Rajski, Jerzy Tyszer, and Nilanjan Mukherjee Acceptance Speech × Pagination « First First page ‹‹ Previous page 1 2 3 ›› Next page Last » Last page
"Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, Issue 10, pp. 1463 - 1475, October 2014
"Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, Issue 10, pp. 1533 - 1545, September 2013
"Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, Issue 12, pp. 1814 - 1827, December 2011
"An Analytical Approach for Network-on-Chip Performance Analysis" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, Issue 12, pp. 2001-2013, December 2010
"Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, Issue 8, pp. 1176-1189, August 2009
"FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 1, pp. 70-83, January 2008
"Systematic and Automated Multiprocessor System Design, Programming, and Implementation" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 3, pp. 542-555, March 2008
"Using Simulation and Satisfiability to Compute Flexibilities in Boolean Networks" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 5, pp. 743-755, May 2006
"On Symbolic Model Order Reduction" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 7, pp. 1257-1272, July 2007
"Embedded Deterministic Test" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 5, pp. 776-792, May 2006