IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award

To recognize the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Historical Background:

The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award is sponsored by the IEEE Council on EDA and recognizes the best paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems publication.

The award is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research. Anyone who is an author of a paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award is eligible for nomination.

Prize:

$500 for each author (maximum of $2,000 per award) and Certificate plaque

Funding:

Funded by the IEEE Council on Electronic Design Automation.

Presentation:

The award will be presented at the ICCAD conference.

Basis for Judgement:

General quality, originality, contributions, subject matter, and timeliness.

Eligibility:

Authors of papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award.

Nomination Details:

Nomination deadline is 28 February of the award year.

View the 2020 Donald O. Pederson Award Committee

Nomination Form:

Nominate for this Award

Recipients

2011

"Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, Issue 8, pp. 1176-1189, August 2009

Amith Singhee

2010

"FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 1, pp. 70-83, January 2008

Chris Chu, and Yiu-Chung Wong

2009

"Systematic and Automated Multiprocessor System Design, Programming, and Implementation"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue 3, pp. 542-555, March 2008

Hristo Nikolov, Todor Stefanov, and Ed F. Deprettere

2008

"Using Simulation and Satisfiability to Compute Flexibilities in Boolean Networks"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 5, pp. 743-755, May 2006

Alan Mishchenko, Jin S. Zhang, Subarna Sinha, Jerry R. Burch, Robert K. Brayton, and Malgorzata Chrzanowska-Jeske

2007

"On Symbolic Model Order Reduction"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 7, pp. 1257-1272, July 2007

Guoyong Shi, Bo Hu, and C.-J. Richard Shi

2006

"Embedded Deterministic Test"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 5, pp. 776-792, May 2006

Mark Kassab, Janusz Rajski, Jerzy Tyszer, and Nilanjan Mukherjee

2005

"X-compact: An Efficient Response Compaction Technique"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 3, pp. 421-432, March 2004

Subhasish Mitra

6 (Western U.S.)

Biography

Subhasish Mitra is currently a Professor of Electrical Engineering and Computer Science at Stanford University, Stanford, CA, USA, where he directs the Stanford Robust Systems Group and co-leads the computation focus area of the Stanford SystemX Alliance. He is also a Faculty Member with the Neurosciences Institute, Stanford University. He holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI, Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation, Santa Clara, CA, USA. His current research interests include broadly across robust computing, nanosystems, VLSI design, validation, test, and electronic design automation, and neurosciences. He along with his students and collaborators demonstrated the first carbon nanotube computer and the first 3-D nanosystem with computation immersed in data storage. These demonstrations received widespread recognitions (cover of Nature, Research Highlight to the U.S. Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, The Economist, Electronic Engineering Times, IEEE Spectrum, MIT Technology Review, National Public Radio, The New York Times, Scientific American, Time, The Wall Street Journal, The Washington Post, and numerous others worldwide). His earlier work on X-Compact test compression has been a key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial electronic design automation tools. He is a Fellow of the Association for Computing Machinery (ACM) and IEEE. He received the Association for Computing Machinery Special Interest Group on Design Automation/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test-of-time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel's highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He along with his students published several award-winning papers at major venues, including the ACM/IEEE Design Automation Conference, the IEEE International Solid-State Circuits Conference, the ACM/IEEE International Conference on Computer-Aided Design, the IEEE International Test Conference, the IEEE Transactions on Computer-Aided Design, the IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. He was honored several times by graduating seniors for being important to them during their time at Stanford. He has served on the Defense Advanced Research Projects Agency's Information Science and Technology Board as an Invited Member.

Affiliation(s)

Stanford University

United States

, and Kee Sup-Kim

2004

"Synthesis of Reversible Logic Circuits"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, Issue 6, pp. 710-722, June 2003

Vivek V. Shende, Aditya K. Prasad, and John P. Hayes

2003

"An Efficient Graph Representation for Arithmetic Circuit Verification"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Issue 12, pp. 1443-1454, December 2001

Yirng-An Chen, and Randal E. Bryant

2002

"Floorplanning Using a Tree Representation"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Issue 2, February 2001

Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng

, and Takeshi Yoshimura