To recognize the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Historical Background: The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award is sponsored by the IEEE Council on EDA and recognizes the best paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems publication. The award is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research. Anyone who is an author of a paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award is eligible for nomination. Prize: $500 for each author (maximum of $2,000 per award) and Certificate plaque Funding: Funded by the IEEE Council on Electronic Design Automation. Presentation: The award will be presented at the ICCAD conference. Basis for Judgement: General quality, originality, contributions, subject matter, and timeliness. Eligibility: Authors of papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award. Nomination Details: Nomination deadline is 28 February of the award year. Nomination Form: Nominate for this Award Recipients 2010 "FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 70-83, January 2008. Chris Chu, and Yiu-Chung Wong Acceptance Speech × 2009 "Systematic and Automated Multiprocessor System Design, Programming, and Implementation" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 542-555, March 2008. Hristo Nikolov, Todor Stefanov, and Ed F. Deprettere Acceptance Speech × 2008 "Using simulation and satisfiability to compute flexibilities in Boolean networks" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 743-755, May 2006. Alan Mishchenko, Jin S. Zhang, Subarna Sinha, Jerry R. Burch, Robert K. Brayton, and Malgorzata Chrzanowska-Jeske Acceptance Speech × 2007 "On Symbolic Model Order Reduction" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1257-1272, July 2007. Guoyong Shi, Bo Hu, and C.-J. Richard Shi Acceptance Speech × 2006 "Embedded Deterministic Test" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 23, no. 5, pp. 776-792, May 2006. Mark Kassab, Janusz Rajski, Jerzy Tyszer, and Nilanjan Mukherjee Acceptance Speech × 2005 "X-compact: An Efficient Response Compaction Technique" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, pp. 421-432 March 2004. Subhasish Mitra, and Kee Sup-Kim Acceptance Speech × 2004 "Synthesis of Reversible Logic Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710-722, June 2003. Vivek V. Shende, Aditya K. Prasad, and John P. Hayes Acceptance Speech × 2003 "An Efficient Graph Representation for Arithmetic Circuit Verification" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp. 1443-1454, December 2001. Yirng-An Chen, and Randal E. Bryant Acceptance Speech × 2002 "Floorplanning Using a Tree Representation" Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, and Takeshi Yoshimura Acceptance Speech × 2001 "SPFD: A New Method to Express Functional Flexibility" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 840-849, August 2000. Shigeru Yamashita, Hiroshi Sawada, and Akira Nagoya Acceptance Speech × Pagination « « First ‹ ‹‹ 1 2 3 › ›› » Last »
"FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 70-83, January 2008.
"Systematic and Automated Multiprocessor System Design, Programming, and Implementation" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 542-555, March 2008.
"Using simulation and satisfiability to compute flexibilities in Boolean networks" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 743-755, May 2006.
"On Symbolic Model Order Reduction" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1257-1272, July 2007.
"Embedded Deterministic Test" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 23, no. 5, pp. 776-792, May 2006.
"X-compact: An Efficient Response Compaction Technique" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 3, pp. 421-432 March 2004.
"Synthesis of Reversible Logic Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710-722, June 2003.
"An Efficient Graph Representation for Arithmetic Circuit Verification" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, pp. 1443-1454, December 2001.
"SPFD: A New Method to Express Functional Flexibility" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 8, pp. 840-849, August 2000.
