Jason Cong Professor UCLA - Computer Science Department IEEE Region: 6 Email Website 2017 Talk(s): Customizable Computing at Datacenter Scale Customizable Computing at Datacenter Scale × In the past decade, CDSC has been exploring customizable computing, which emphasizes extensive use of customized accelerators on programmable fabrics for much greater performanc and energy efficiency. With Intel’s $17B acquistion of Altera in 2015 and Amazon’s introduction of FPGAs in its AWS public cloud in 2017, customizable computing is going from advanced research into mainstream computing. Although the performance and energy efficiency benefits have been clearly demonstrated, a significant challenges, however, is the efficient design and implementation of various acceleration on FPGAs, which is a barrier to many software programmers. In this talk, I shall talk about our effort on developing an automated compilation flow from high-level programming languages to FPGAs. I start with a quick review of our early work on high-level synthesis. Then, I shall present our recent effort on source-code level transformation and optimization for customizable computing, including support of high-level domain-specific languages (DSL) for deep learning (with Caffe or TensorFlow), imaging processing (with Halide), and big-data processing (with Spark), and support automated compilation to customized micro-archictecture templates, such as systolic arrays, stencils, and CPP (composable parallel and pipelined). High-Level Synthesis and Beyond High-Level Synthesis and Beyond × Automatic Customizable Computing: From DSLs to FPGAs for Deep Learning and Beyond Automatic Customizable Computing: From DSLs to FPGAs for Deep Learning and Beyond × In SOCC’2006, my group presented an invited paper on xPilot – the high-level synthesis (HLS) tool developed at UCLA for automatic synthesis of behavior-level C/C++ specifications into highly optimized RTL code. In the same year, The startup company AutoESL was formed to commercialize our research on HLS – an effort that many EDA companies tried but failed for over two decades. Nevertheless, the AutoESL tool (renamed to Vivado HLS after Xilinx acquisition in 2011) becomes probably the most successful and widely used HLS tool for FPGAs. As we come to the end of Moore’s Law scaling, HLS plays a critical role in enabling customizable computing, which emphasizes extensive use of customized accelerators on programmable fabrics for much greater performance and energy efficiency. With Intel’s $17B acquisition of Altera in 2015 and Amazon’s introduction of FPGAs in its AWS public cloud in 2017, customizable computing is going from advanced research into mainstream computing. In this talk, I shall first review the progress we made on HLS. Then, I talk about our effort on developing an automated compilation flow from high-level programming languages to FPGAs for customizable computing. I shall present our recent effort on source-code level transformation and optimization for customizable computing, including support of high-level domain-specific languages (DSL) for deep learning (with Caffe or TensorFlow), imaging processing (with Halide), and big-data processing (with Spark), and exploration of microarchitecture templates, such as systolic arrays, stencils, and CPP (composable parallel and pipelined), for efficient support of these application domains.
