Xiaobo Sharon Hu

As Moore’s Law based device scaling and accompanying performance scaling trends are slowing down, there is increasing interest in new technologies and computational models for fast and more energy-efficient information processing. Meanwhile, there is growing evidence that, with respect to traditional Boolean circuits and von Neumann processors, it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Nevertheless, some beyond-CMOS devices demonstrate other unique characteristics such as ambipolarity, negative differential resistance, hysteresis, and oscillatory behavior. Exploiting such unique characteristics, especially in the context of alternative circuit and architectural paradigms, has the potential to offer orders of magnitude improvement in terms of power, performance, and capability.

In order to take full advantage of beyond-CMOS devices, however, it is no longer sufficient to develop algorithms, architectures, and circuits independent of one another. Cross-layer efforts spanning from devices to circuits to architectures to algorithms are indispensable. This talk will examine energy-efficient neural network accelerators for embedded applications in this context. Several deep neural network accelerator designs based on cross-layer efforts spanning from alternative device technologies, circuit styles and architectures will be highlighted. A comprehensive application-level benchmarking study for the MNIST dataset will be presented. The discussions will demonstrate that cross-layer efforts indeed can lead to orders of magnitude gain towards achieving extreme scale energy-efficient processing.

The inevitable slowdown of the CMOS scaling trend has fueled an explosion of research endeavors in finding a CMOS replacement. However, recent studies suggest that many of the emerging devices being investigated, if used as simple drop-in replacement for MOSFETs, may only achieve speedups that mirror historical trends in the best case. The consensus from the community is that cross-layer efforts are essential in combating the CMOS scaling challenge with emerging devices. This talk presents such an effort centered around a particular emerging device, ferroelectric FETs (FeFETs).

An FeFET is made by integrating a ferroelectric material layer in the gate stack of a MOSFET. It is a non- volatile device that can behave as both a transistor and a storage element. This unique property of FeFETs enables area efficient and low-power fine-grained logic-in-memory, which are desirable for many data analytic and machine learning applications. This presentation will elaborate novel circuits based on FeFETs to accomplish basic logic-in-memory operations, ternary content addressable memory (TCAM) as well as FeFET based crossbars for binary Convolutional Neural Networks. Comparisons of these FeFET based circuits with other alternative technologies will be discussed.

Wireless networked control systems (WNCSs) are fundamental to many Internet-of-Things (IoT) applications and must work under real-time constraints in order to ensure timely collection of environmental data and proper delivery of control decisions. The Quality of Service (QoS) offered by a WNCS is thus often measured by how well it satisfies the end-to-end deadlines of the real-time tasks executed in the WNCS. Network resource management in WNCSs plays a critical role in achieving the desired QoS. Unexpected internal and external disturbances that may appear in WNCSs concurrently make resource management inherently challenging. The explosive growth of IoT applications especially in terms of their scale and complexity further exacerbate the level of difficulty in network resource management.

In this talk, I first give a general introduction of WNCSs and the challenges that they present to network resource management. In particular, I will discuss the complications due to external disturbances and the need for dynamic data-link layer scheduling. I then highlight our recent work that aims at tackling this challenge. Our work balances the scheduling effort between a gateway (or access points) and the rest of the nodes in a network. It paves the way towards decentralized network resource management in order to achieve scalability. Experimental implementation on a wireless testbed further validates the applicability of our proposed techniques. I will end the talk outlining our on-going effort in this exciting and growing area of research.