Institution: Qualcomm Technologies, Inc. Job Location: California: San Diego and San Jose Posted: 2019-08-21 Position: IC Package System Designer for AI chips Description: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. The IC Package Architecture and Design Team at Qualcomm has an opening for an experienced package Design Engineer for AI chips. This team is responsible for road mapping, architecture, design methodology, design implementation and verification for all Qualcomm package products. Team is looking for experienced packaging/system engineer who can own the packaging roadmap for AI packages and can select and define the package and design substrates for flip-chip designs for AI packages. Select the IC package type /area/ based on IC requirements/cost requirements/ based on requirements for footprint, mechanical, thermal and electrical performance with the goal to achieve lowest system-level cost Design the IC package pinmap and release the substrate for IC package design for manufacturing Work with IC teams to define the bump patterns based on die-level floor plan and macroblock placement Perform Signal integrity/ PDN/ analysis for the IC package Review different SIP/Module partition experience Partner with Packaging suppliers and review their roadmap to pitch the best package technology for the AI roadmap Define package roadmap for future generation of AI packages based on industry survey/IC roadmap/memory partitioning Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. 7+ years Hardware Engineering experience or related work experience. Preferred Qualifications 7 to 15 years of IC package design or PCB design and/or modeling experience Hands on experience with Cadence SIP and/or Mentor Xpedition. Knowledge of assembly and substrate manufacturing processes Fundamental understanding of Signal Integrity and PDN. Pkg/PCB SI/PI modeling, co-simulation and analysis experience is a plus. Familiar with PCB design and or stackup and breakout constraints Experience in schematic capture, layout and design using Cadence Allegro/Mentor Schematic Design - Entry (Concept HDL) design tools is a plus Education Requirements Master's/PhD is preferred EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification. If you need an accommodation during the application/hiring process, you may request an accommodation by sending an email to [email protected]. Resource Links: Apply Now
