Presentation Library

Webinar

CAD For Assurance: RTL Logic Attacks and SMT Attack

Chandan Karfa , Avesta Sasan

Webinar

CAD for Assurance: NETA Toolset and FEDS, SAFARI, XFC

Dr. Travis Meade

, Jim Geist

, Chester Rebeiro

Webinar

DAWN: Quantum Computing & Design Automation Challenges & Opportunities

Oliver Dial , Ross Duncan , Carmen G. Almudever

, Robert Wille

Robert Wille

8 (Africa, Europe, Middle East)

Biography

From 2002 to 2006, Robert Wille studied Computer Science (Diploma) at the University of Bremen. After successfully completing his doctorate in 2009 (summa cum laude), he worked as a postdoc at the University of Bremen and, since 2013, as Senior Researcher in the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). Besides that, he served as a lecturer at the University of Applied Science Bremen from 2010 to 2012 and was a guest professor for Technical Computer Science at the University of Potsdam in 2012 as well as for Embedded Systems at the Technical University of Dresden in 2013/2014. In 2014, he completed his habilitation and, since October 2015, he is a full professor at the Johannes Kepler University Linz and head of the Institute for Integrated Circuits.

Robert Wille’s expertise is in the development of design technologies for various application areas – with a particular focus on the design, verification, and test of circuits and systems. He considers conventional as well as emerging computing technologies such as quantum computation, reversible circuits, or microfluidic biochips. Since 2007, Robert Wille published more than 200 journal and conference papers in this area (including top-notch venues such as DAC, DATE, ICCAD, ASP-DAC, MoDELS, or TCAD) and was repeatedly awarded (e.g. with a Google Research Award in 2018 as well as Best Paper Awards at the International Conference on Computer-Aided Design in 2013 and the Forum on Specification and Design Languages in 2010).

Robert Wille served as Associate Editor and Guest Editor for various renowned journals such as the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), the ACM Journal on Emerging Technologies in Computing Systems (JETC), or Springer’s Lecture Notes in Computer Science (LNCS). Additionally, he was General Chair and PC Chair at several conferences such as at the Forum on Description Languages, the Conference on Reversible Computation, and the International Symposium on Multiple-Valued Logic (ISMVL) as well as served as Subcommittee Chair at the Asia and South Pacific Design Automation Conference (ASP-DAC), was in program committees of numerous conferences such as ASP-DAC, DAC, DATE, ICCAD, ISMVL, etc., and organized several conferences, tutorials, Dagstuhl seminars, workshops, and special sessions.

Affiliation(s)

Johannes Kepler University

Austria

Webinar

DAWN: Publishing in EDA Transactions, Journals, and Magazines

Hai (Helen) Li

, Rajesh K. Gupta

Rajesh K. Gupta

6 (Western U.S.)

Biography

Rajesh K. Gupta (F’91) received the B.Tech. degree in electrical engineering from Indian Institute of Technology Kanpur, Kanpur, India, in 1984, the M.S. degree in EECS from University of California, Berkeley, Berkeley, CA, USA, in 1986, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, USA, in 1994.

He is a Qualcomm Endowed Chair Professor with the Department of Computer Science and Engineering, University of California, San Diego, San Diego, CA, USA. He was a Circuit Designer with Intel Corporation, Santa Clara, CA, USA, as a member of three successful processor design teams and on the Computer Science Faculty, University of Illinois, Urbana-Champaign, Champaign, IL, USA and the University of California, Irvine, Irvine, CA, USA. Regardless of the title, the focus of the research has been on methods and tools to make things better, such as, more energy-efficient and reliable, or enable others (mostly, designers and architects) to do things better. To the extent a problem area requires it, there is a focus on creating usable artifacts or at least find the limits on what is achievable in practice. His past contributions include SystemC modeling and SPARK parallelizing high-level synthesis, both of which have been incorporated into industrial practice. His publications and patents cover various aspects of embedded systems design, design automation, clock design, data-path synthesis, system-on-chip modeling, and dynamic power management. He was a Lead or a Co-Lead of DARPA-sponsored efforts under the data-intensive systems and power-aware computing and communications programs on the role of adaptation in energy-efficient system architectures. His ongoing projects are focused on efficient compositional synthesis of system-chips, microelectronic variability, accurate timing, and synchronization for the integrated systems. His current research interests include embedded,cyber-physical systems, and Internet-of-Things.

Dr. Gupta was a recipient of the Best Demonstration Paper Award at ACM BuildSys’16, the Best Paper Award at IEEE/ACM DCOSS’08, and the Best Demonstration Award at IEEE/ACM IPSN/SPOTS’05 with and his students. He is a fellow of the ACM.

Affiliation(s)

University of California, San Diego

United States

, Xiaobo Sharon Hu

, Tulika Mitra

, Ramesh Karri

Ramesh Karri

1 (Northeastern U.S.)

Biography

Ramesh Karri is a Professor of Electrical and Computer Engineering at Tandon School of Engineering, New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research and education activities span hardware cybersecurity including trustworthy ICs, processors and cyber-physical systems; security-aware computer-aided design, test, verification, validation and reliability; nano meets security; metrics; benchmarks; hardware cybersecurity competitions; additive manufacturing security.

He has over 200 journal and conference publications including tutorials on Trustworthy Hardware in IEEE Computer (2) and Proceedings of the IEEE (5). His groups work on hardware cybersecurity was nominated for best paper awards (ICCD 2015 and DFTS 2015) and received awards at conferences (ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012) and at competitions (ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge).

He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cybersecurity of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Co-founded the NYU Center for CyberSecurity -CCS (cyber.nyu.edu), co-founded the Trust-Hub (trust-hub.org/) and founded and organizes the Embedded Security Challenge, the annual red team blue team event at NYU, (www.nyu.edu/csaw2016/csaw-embedded).

He co-founded the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as program/general chair of conferences including IEEE International Conference on Computer Design (ICCD), IEEE Symposium on Hardware Oriented Security and Trust (HOST), IEEE Symposium on Defect and Fault-Tolerant Nano VLSI Systems (DFTS) NANOARCH, RFIDSEC 2015 and WISEC 2015. He serves on several program committees (DAC, ICCAD, HOST, ITC, VTS, ETS, ICCD, DTIS, WIFS).

He was the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-present), ACM Journal of Emerging Computing Technologies (2007-present), ACM Transactions on Design Automation of Electronic Systems (2014-present), IEEE Access (2015-present), IEEE Transactions on Emerging Technologies in Computing (2015-present), IEEE Design and Test (2015-present) and IEEE Embedded Systems Letters (2016-present). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He is on the Executive Committee of IEEE/ACM Design Automation Conference initiating and leading the [email protected] initiative (2014-2017). He has delivered invited keynotes, talks, and tutorials on Hardware Security and Trust (ESRF, DAC, DATE, VTS, ITC, ICCD, NATW, LATW, CROSSING etc).

Affiliation(s)

New York University

United States

, Jörg Henkel

Jörg Henkel

8 (Africa, Europe, Middle East)

Biography

Prof. Jörg Henkel is with Karlsruhe Institute of Technology (KIT), Germany, where he is directing the Chair for Embedded Systems CES. Before, he was a Senior Research Staff Member at NEC Laboratories in Princeton, NJ. He received his PhD from Braunschweig University with "Summa cum Laude".

Prof. Henkel has/is organizing various embedded systems and low power ACM/IEEE conferences/symposia as General Chair and Program Chair and was a Guest Editor on these topics in various journals like the IEEE Computer Magazine.

He was Program Chair of CODES'01, RSP'02, ISLPED’06, SIPS'08, CASES'09, Estimedia'11, VLSI Design'12, ICCAD’12, PATMOS’13, NOCS’14 and served as General Chair for CODES'02, ISLPED’09, Estimedia’12, ICCAD’13 and ESWeek'16. He is/has been a steering committee member of major conferences in the embedded systems field like at ICCAD, ESWeek, ISLPED, Codes+ISSS, CASES and is/has been an editorial board member of various journals like the IEEE TVLSI, IEEE TCAD, IEEE TMSCS, ACM TCPS, JOLPE, etc.

In recent years, Prof. Henkel has given more than ten keynotes at various international conferences primarily with focus on embedded systems dependability. He has given full/half-day tutorials at leading conferences like DAC, ICCAD, DATE, etc. Prof. Henkel received the 2008 DATE Best Paper Award, the 2009 IEEE/ACM William J. Mc Calla ICCAD Best Paper Award, the Codes+ISSS 2015, 2014, and 2011 Best Paper Awards, and the MaXentric Technologies AHS 2011 Best Paper Award as well as the DATE 2013 Best IP Award and the DAC 2014 Designer Track Best Poster Award. He is the Chairman of the IEEE Computer Society, Germany Section, and was the Editor-in-Chief of the ACM Transactions on Embedded Computing Systems (ACM TECS) for two consecutive terms.
He is an initiator and the coordinator of the German Research Foundation's (DFG) program on 'Dependable Embedded Systems' (SPP 1500). He is the site coordinator (Karlsruhe site) of the Three-University Collaborative Research Center on "Invasive Computing" (DFG TR89). He is the Editor-in-Chief of the IEEE Design&Test Magazine. He holds ten US patents and is a Fellow of the IEEE.

Affiliation(s)

Karlsruhe Institute of Technology (KIT)

Germany

Webinar

DAWN: Secure Silicon Recent Developments and Upcoming Challenges

Mark M. Tehranipoor , Gang Qu

, Brandon Wang

, Ahmad-Reza Sadeghi

Webinar

DAWN: Career Development for Scholars in EDA Research

Diana Marculescu

, Kwang-Ting Tim Cheng

, Giovanni De Micheli

Giovanni De Micheli

8 (Africa, Europe, Middle East)

Website

Biography

Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).

Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 750 technical articles. His citation h-index is 92 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics.

Prof. De Micheli is the recipient of the 2016 IEEE/CS Harry Goode award for seminal contributions to design and design tools of Networks on Chips, the 2016 EDAA Lifetime Achievement Award, the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools and the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received also the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000, the D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS in 1987, and several Best Paper Awards, including DAC (1983 and 1993), DATE (2005), Nanoarch (2010 and 2012) and Mobihealth(2016).

He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1997-2001). He has been Chair of several conferences, including Memocode (2014) DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989).

Affiliation(s)

EPFL

Switzerland

, Ayse Coskun

, Phillip Stanley-Marbell

, Jeyavijayan Rajendran

Webinar

DAWN: Machine Learning for EDA

Azalia Mirhoseini

, Anna Goldie

, David Pan

, Jiang Hu

, Song Han , Shao-Yun Fang

Conference Special Session

New Directions in Distributed Deep Learning: Bringing the Network at Forefront of IoT Design

Radu Marculescu

Conference Special Session

Building E2E IoT Applications with QoS Guarantees

Selma Saidi

Conference Special Session

In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview

Kaushik Ravindran

Conference Special Session

Machine Learning Based Sice Channel Attacks and Countermeasures

Marilyn Wolf

Conference Special Session

Autonomous Warehouse-Scale Computers

Parthasarathy Ranganathan

Biography

Parthasarathy (Partha) Ranganathan is currently at Google designing their next-generation systems. Before this, he was a HP Fellow and Chief Technologist at Hewlett Packard Labs where he led their research on systems and datacenters. Dr. Ranganathan's research interests are in systems architecture and manageability, energy-efficiency, and systems modeling and evaluation. He has done extensive work in these areas including key contributions around energy-aware user interfaces, heterogeneous multi-core processors, power capping and power-aware server designs, federated enterprise power management, energy modeling and benchmarking, disaggregated blade server architectures, and most recently, storage hierarchy and systems redesign for non-volatile memory. He was also one of the primary developers of the publicly distributed Rice Simulator for ILP Multiprocessors (RSIM). Dr. Ranganathan's work has led to broad impact on both academia and industry including several commercial products such as Power Capping and HP Moonshot servers. He holds more than 50 patents (with another 45 pending) and has published extensively, including several award-winning papers. He also teaches regularly (including, most recently, at Stanford) and has contributed to several popular computer architecture textbooks. Dr. Ranganathan and his work have been featured on numerous occasions in the press including the New York Times, Wall Street Journal, Business Week, San Francisco Chronicle, Times of India, Slashdot, Youtube, and Tom's hardware guide. Dr. Ranganathan has been named one of the world's top young innovators by MIT Technology Review, as one of the top 15 enterprise technology rock stars by Business Insider, and has been recognized with several other awards including the ACM SIGARCH Maurice Wilkes award and Rice University's Outstanding Young Engineering Alumni award. Dr. Ranganathan received his B.Tech degree from the Indian Institute of Technology, Madras and his M.S. and Ph.D. from Rice University, Houston. He is also an ACM and IEEE Fellow.

Affiliation(s)

Distinguished Engineer

Google

United States

Conference Special Session

Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs

Jürgen Teich

Conference Special Session

Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs

Michael Kishinevsky

Conference Special Session

Efficient Synthesis of Compact Deep Neural Networks

Niraj K. Jha

1 (Northeastern U.S.)

Biography

Niraj K. Jha (S’85-M’85-SM’93-F’98) received the BTech degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 1981, the MS degree in electrical engineering from S.U.N.Y. at Stony Brook, New York, in 1982, and the PhD degree in electrical engineering from the University of Illinois at Urbana-Champaign, Illinois, in 1985.

He is a professor of electrical engineering with Princeton University. He received the Distinguished Alumnus Award from I.I.T., Kharagpur in 2014. He is a recipient of the AT&T Foundation Award, NEC Preceptorship Award for research excellence, NCR Award for teaching excellence, six School of Engineering and Applied Sciences Teaching Commendations, and Princeton University Graduate Mentoring Award.

He has served as the editor-in-chief of the IEEE Transactions on VLSI Systems and an associate editor of the IEEE Transactions on Circuits and Systems I and II, the IEEE Transactions on VLSI Systems, the IEEE Transactions on Computer-Aided Design, the IEEE Transactions on Computers, the Journal of Electronic Testing: Theory and Applications, and the Journal of Nanotechnology. He is currently serving as an associate editor of the IEEE Transactions on Multi-Scale Computing Systems and the Journal of Low Power Electronics. He has served as the program chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004 International Conference on Embedded and Ubiquitous Computing, and the 2010 International Conference on VLSI Design, as the director of the Center for Embedded System-on-a-chip Design funded by New Jersey Commission on Science and Technology, as the associate director of the Andlinger Center on Energy and the Environment, and on the program committees of more than 170 conferences and workshops. His research interests include embedded computing, secure computing, machine learning, monolithic 3D IC design, low power hardware/software design, and computer-aided design of integrated circuits and systems. He has given several keynote speeches in the areas of nanoelectronic design/test and embedded systems. He is a fellow of the IEEE and ACM

Affiliation(s)

Princeton University

United States

Conference Special Session

Creating an Agile Hardware Design Flow

Priyanka Raina

Conference Special Session

Chipyard - Integrated SoC Design, Simulation, Implementation Environment

Krste Asanović

Conference Special Session

Developing Privacy-Preserving AI Systems: The Lessons Learned

Rosario Cammarota

Conference Special Session

Computational Methods for Biological Exploration

Louis Scheffer

Biography

For more than two decades Louis Scheffer has been working to improve the design of microchips, figuring out how to connect hundreds of thousands of electronic transistors in a single device. At Janelia, he is now applying similar design principles to understand another type of “wiring”—the intricate interconnections that neurons make in the brain.

Neuroscientists want to map the flow of electrical signals in the brain to understand how it turns signals from the eyes into images, for example, or instructs arms and legs to move. But these neuronal circuits are difficult to map, especially when dealing with billions of neurons as in the human brain. For each neuron, researchers have to follow its long projections—the axons and dendrites—and determine which other neurons they connect with.

One way to accomplish the task is to take pictures of the neurons with powerful microscopes and visually follow their tortuous paths. To do so, tiny slices— 1/1000th the thickness of a human hair—of an organism’s brain are photographed with an electron microscope (EM). Images are then stacked on top of each other, and individual neurons and their connections are followed from one image to the next, often through thousands of layers of brain tissue. “You have to try to reconstruct three-dimensional images and see the connections from one neuron to another,” explains Scheffer.

Even when dealing with relatively small brains, like that of the fruit fly Drosophila melanogaster, generating a map of the brain’s wiring is a daunting task. Just to reconstruct the three-dimensional neuronal networks in the medulla—one of the brain regions that receives visual signals from the eyes—takes about 153,000 EM images. “That’s how many images you need to analyze to be able to study one part of the optic system, in one eye of one small fly,” says Scheffer.

To analyze each image from scratch would take researchers at least 10 hours. But researchers rely on computers to do a “first pass” analysis of the images. Then the researchers go back to “proofread” the computer’s interpretation, spending about one hour on each image. “We do the best job we can with the software available and then have to correct errors manually,” explains Scheffer. “The proofreading is the rate-limiting step.”

To cut down on proofreading time, Scheffer and others are trying to develop software to help computers perform the reconstruction step more accurately and efficiently. In particular, he wants to teach computers to recognize different types of neurons and the axons and dendrites shooting out of them. “Neuroscientists are good at identifying different neurons in EM images and determining which neurons are the same ones in different images,” says Scheffer. “We want to transfer this kind of knowledge into computer programs.”

At the Janelia campus, Scheffer says he has immediate access to neuroscientists who can test out his software as it is being developed. “They are right next door,” says Scheffer. “When it does not work, they come pounding on my door.”

An electrical engineer, Scheffer’s journey to Janelia was somewhat serendipitous. While planning a conference in Paris in 2004 that focused on interconnections in computers, one of his colleagues told him about the work of Janelia group leader Dmitri Chklovskii, who was studying interconnections in the brain. “I invited him to give a talk, and everyone thought it was really interesting,” say Scheffer. “So, I invited him to two other conferences, and then he invited me to talk at Janelia.”

Scheffer was immediately drawn to the multidisciplinary nature of Janelia. “I had never done research in biology, so the biology part of my work has been a steep learning curve. When people start talking about GAL4 and flip-out mutants, I have to stop and think,” says Scheffer. “But the software part is very similar to the software for engineering.”

His aim is to map all the neurons in the fly brain in the next five years. That may seem like an ambitious goal, but Scheffer is optimistic that it will get done. “When I started in the transistor field in 1981, it took me two years to build a chip with 15,000 transistors in it,” he explains. “By 2009, we had developed software that could help build a chip with 1 billion transistors in the same amount of time.” He is confident of seeing similar advances in researchers’ ability to map the brain’s functions.

Affiliation(s)

Howard Hughes Medical Institute

United States

Janelia Research Campus

Video Lecture

Current Progress in Quantum Computing

Paul Nation

CAD for Assurance

CAD For Assurance: RTL Logic Attacks and SMT Attack

CAD for Assurance: NETA Toolset and FEDS, SAFARI, XFC

DAWN

DAWN: Quantum Computing & Design Automation Challenges & Opportunities

DAWN: Publishing in EDA Transactions, Journals, and Magazines

DAWN: Secure Silicon Recent Developments and Upcoming Challenges

DAWN: Career Development for Scholars in EDA Research

DAWN: Machine Learning for EDA

DAC 2020

New Directions in Distributed Deep Learning: Bringing the Network at Forefront of IoT Design

Building E2E IoT Applications with QoS Guarantees

In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview

Machine Learning Based Sice Channel Attacks and Countermeasures

Autonomous Warehouse-Scale Computers

Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs

Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs

Efficient Synthesis of Compact Deep Neural Networks

Creating an Agile Hardware Design Flow

Chipyard - Integrated SoC Design, Simulation, Implementation Environment

Developing Privacy-Preserving AI Systems: The Lessons Learned

Computational Methods for Biological Exploration

ICCAD 2019

Current Progress in Quantum Computing

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