Learning and adaptation are key to natural and artificial intelligence in complex and variable environments. Neural computation and communication in the brain are partitioned into the grey matter of dense local synaptic connectivity in tightly knit neuronal networks, and the white matter of sparse long-range connectivity over axonal fiber bundles across distant brain regions. This exquisite distributed multiscale organization provides inspiration to the design of scalable neuromorphic systems for deep learning and inference, with hierarchical address event-routing of neural spike events and multiscale synaptic connectivity and plasticity, and their efficient implementation in silicon low-power mixed-signal very-large-scale-integrated circuits. Advances in machine learning and system-on-chip integration have led to the development of massively parallel silicon learning machines with pervasive real-time adaptive intelligence at nanoscale that begin to approach the efficacy and resilience of biological neural systems, and already exceed the nominal energy efficiency of synaptic transmission in the mammalian brain. I will highlight examples of neuromorphic learning systems-on-chips with applications in template-based pattern recognition, vision processing, and human-computer interfaces, and outline emerging scientific directions and engineering challenges in their large-scale deployment.
Recent years have seen an explosion in the cost and time required to design advanced System-on-Chips (SoCs), systems-in-packages (SiPs), and PCBs. As part of the $1.5B Electronics Resurgence Initiative (ERI), DARPA is building the world's first general purpose silicon compilers. The effort involves two distinct research programs, the Intelligent Design of Electronic Assets (IDEA) program aiming to create a no-human-in-the-loop layout generator for digital and analog circuits, and the Posh Open Source Hardware (POSH) program aiming to create a high quality trustable open source ecosystem. Together the efforts will create a universal hardware compiler capable of automatically generating production ready GDSII drawings directly from a rich catalog of trustable source code and schematics for digital as well as analog circuits. Achieving this ambitious goal will require advancing the state of the art in machine learning, optimization algorithms, expert systems, and verification technology. This talk will discuss technical challenges associated with building a universal hardware compiler and provide analysis of potential economic and societal impacts.