Special Issue on Architecture Advances Enabled by Emerging Technologies

Aim and Scope

As Moore’s Law-based scaling trends for CMOS technology begin to slow down, in order to continue the impressive improvements in von Neumann processor performance, more efforts and resources are being devoted to the exploration of technologies that can potentially replace and/or complement CMOS. At present, numerous beyond-CMOS technologies (i.e., based on different materials and/or device concepts) are being investigated. Examples include tunneling transistors, spintronic or magnetoelectric devices, etc. However, various benchmarking efforts have shown that, with respect to traditional Boolean circuits and von Neumann architectures, it may be challenging for emerging devices to compete with the CMOS technology. 

Alternatively, many beyond-CMOS devices exhibit unique characteristics that may enable novel circuits and architectures (as well as accompanying performance enhancements) that are simply not possible with CMOS alone. For example, researchers have used STT-MRAM to develop non-volatile, energy-efficient logic-in-memory arrays for data intensive applications. ReRAM-based spiking neural networks represent another example of matching emerging device characteristics with advanced architectures. Finding the right match between devices and architectures – such that the end products can benefit a large number of applications – is an ambitious goal that has now garnered the attention of researchers from the device, circuit, and architecture communities. 

The aim of this special issue is to feature exciting results at the intersection of device, circuit, and architecture research. We seek contributions that offer new approaches for exploiting unique features of emerging, beyond-CMOS devices at the circuit and architectural levels. Papers describing results that could potentially impact broad application spaces are especially encouraged. Papers that consider tradeoffs between more device/circuit centric figures of merit (e.g., energy and delay) in conjunction with more application-level figures of merit (e.g., inference accuracy) are also especially encouraged.

Topics of Interest

Submissions should be based on work that exploits beyond-CMOS devices at the circuit/architecture level. Pure device-level results will not be considered. On the other hand, pure architecture-level work without connections to emerging devices is also not appropriate for this special issue. Topics of interests include but are not limited to the following:

  • Neuromorphic architectures/circuits based on emerging technologies
  •  In-/near-memory-computing architectures based on emerging technologies
  • Approximate/stochastic computing architectures and systems with emerging technologies
  • Heterogeneous and/or accelerator-based systems (in both 2D and 3D) that employ emerging technologies
  • Holographic and/or optically-inspired computing architectures and interconnect
  • Ising machines based on emerging devices for NP-hard/combinatorial optimization problems
  • Energy conserving oscillatory networks
  • Emerging technology enabled reconfigurable computing architectures
  • Hardware realization of quantum computing

Important Dates

  • Manuscript submission October 15, 2017
  • First round of reviews December 15, 2017
  • Second round of reviews April 30, 2018
  • Final Manuscript November 15, 2018

Submission Website

Guest Editors

An Chen, Semiconductor Research Corporation, Durham, NC, USA 
Vivek De, Intel, Hillsboro, OR, USA 
X. Sharon Hu, University of Notre Dame, IN, USA
Michael Niemier, University of Notre Dame, IN, USA

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Design&Test is a co-sponsored publication of IEEE CEDA, SSCS, and CASS.