Embedded Security
Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation
The emerging security threats in the integrated circuit supply chain do not only challenge the chip integrity, but also raise serious concerns on hardware intellectual property (IP) piracy. Hardware design obfuscation is a promising countermeasure to resist reverse engineering attacks and IP piracy. The majority of existing hardware ob...
By J. Dofe , Q. Yu
A Single Layer 3-D Touch Sensing System for Mobile Devices Application
Touch sensing has been widely implemented as a main methodology to bridge human and machine interactions. The traditional touch sensing range is 2-D and therefore limits the user experience. To overcome these limitations, we propose a novel 3-D contactless touch sensing called Airtouch system, which improves user experience by remotely...
By L. Du , C.-C. Liu , Y. Zhang , Y. Li , Y. Du , Y.-C. Kuan , M.-C. F. Chang
Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures
Large scale many-core systems are able to execute concurrently changing mixes of different parallel applications. Hybrid application mapping combines the strengths of design-time exploration/analysis of resource constellations for task-to-core mappings with the flexibility of choosing concrete mappings at run time. However, state-of-th...
By T. Schwarzer , A. Weichslgartner , M. Glas , S. Wildermann , P. Brand , J. Teich
Emerging Technologies and Applications
A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar
Alternatives to CMOS logic circuit implementations are under research for future scaled electronics. Memristor crossbar-based logic circuit is one of the promising candidates to at least partially replace CMOS technology, which is facing many challenges such as reduced scalability, reliability, and performance gain. Memristor crossbar ...
By L. Xie , H. A. Du Nguyen , M. Taouil , S. Hamdioui , K. Bertels
A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits
Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for...
By A. N. Nagamani , S. N. Anuktha , N. Nanditha , V. K. Agrawal
Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays
Spin transfer torque magnetic random access memory (STT-MRAM) is an emerging memory technology which exhibits nonvolatility, high density, high endurance, and nano-second read and write times. These characteristics make STT-MRAM suitable for last-level cache and other embedded applications. The STT-MRAM bit-cell consists of a magnetic ...
By I. Yoon , A. Raychowdhury
FPGAs and Reconfigurable Systems
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms
Field programmable gate arrays (FPGAs) are often used to accelerate multiple tasks simultaneously, working in a tightly coupled processor-coprocessor architecture. Recently, with the fast development of emerging memory technologies, multicontext FPGAs with high-density memories that support fast dynamic reconfiguration have become feas...
By H. Liang , S. Sinha , W. Zhang
Modeling and Simulation
xMAS-Based QoS Analysis Methodology
On-chip communication system design starting from a high-level model can facilitate formal verification of system properties, such as safety and deadlock freedom. Yet, analyzing its quality-of-service (QoS) property, in our context, per-flow delay bound, is an open challenge. Based on executable micro-architectural specification (xMAS)...
By Z. Lu , X. Zhao
Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms
Analog components are fundamental blocks of smart systems, as they allow a tight interaction with the environment, in terms of both sensing/actuation and communication. This impacts on the design of the overall system, and mainly on the validation phase, that thus requires the joint simulation of digital and analog aspects. In this sce...
By M. Lora , S. Vinco , E. Fraccaroli , D. Quaglia , F. Fummi
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning
At submicrometer manufacturing technology nodes, process variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin to maintain yield, leading to an unaffordable overdesign. Most of these margins, however, are wasted after manufacturing, because process variations cause ...
By G. L. Zhang , B. Li , J. Liu , Y. Shi , U. Schlichtmann
Physical Design
Global Routing With Timing Constraints
We show how to incorporate global static timing constraints into global routing. Our approach is based on the min°Vmax resource sharing model that proved successful for global routing in theory and practice. Static timing constraints are modeled by a linear number of additional resources and customers. The algorithm dynamically adjusts...
By S. Held , D. Muller , D. Rotter , R. Scheifele , V. Traub , J. Vygen
System-Level Design
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators
Graph applications have been gaining importance in the last decade due to emerging big data analytics problems such as Web graphs, social networks, and biological networks. For these applications, traditional CPU and GPU architectures suffer in terms of performance and power consumption due to irregular communications, random memory ac...
By A. Ayupov , S. Yesil , M. M. Ozdal , T. Kim , S. Burns , O. Ozturk
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays
Memory bandwidth bottlenecks severely restrict parallel access of data elements from data arrays. To realize high throughput out of a relatively low bandwidth, memory partitioning algorithms have been proposed to separate data arrays into multiple memory banks, from which multiple data can be accessed in parallel. However, previous par...
By S. Yin , Z. Xie , C. Meng , P. Ouyang , L. Liu , S. Wei
Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning
Cache replacement policies and cache partitioning are well-known cache management techniques which aim to eliminate inter- and intra-application contention caused by co-running applications, respectively. Since replacement policies can change applications°¶ behavior on a shared last-level cache, they have a massive impact on cache part...
By B. Lee , K. Kim , E.-Y. Chung
TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion
The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern of system-on-chip designers. Ultralow power (ULP) very large-scale integration circuits have been receiving considerable interest from both academia and industry as the best-suited techniques for IoT devices, which ca...
By K. Han , J.-J. Lee , J. Lee , W. Lee , M. Pedram
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism
With the explosive growth in the data volume, the I/O bottleneck has become an increasingly daunting challenge for big data analytics. It is urgent and important to introduce high-performance flash-based solid state drives (SSDs) into the storage systems. However, since the existing systems are primarily designed for conventional magne...
By B. Mao , S. Wu , L. Duan
Test
Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications
Image processing circuits are expected to play an important role in Internet of Things electronic systems. For this type of circuits, errors (e.g., those due to wear out) might not be perceptible to us due to our insensitivity to small variances in images or colors. In the case that errors are acceptable (imperceptible), the systems ar...
By T.-Y. Hsieh , Y.-H. Peng , K.-C. Cheng
Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores
Radiation-induced soft errors are a major reliability concern in circuits fabricated at advanced technology nodes. Online soft-error vulnerability estimation offers the flexibility of exploiting dynamic fault-tolerant mechanisms for cost-effective reliability enhancement. We propose a generic run-time method with low area and power ove...
By A. Vijayan , S. Kiamehr , M. Ebrahimi , K. Chakrabarty , M. B. Tahoori
Short Paper
A Library for Combinational Circuit Verification Using the HOL Theorem Prover
Interactive theorem provers can overcome the scalability limitations of model checking and automated theorem provers by verifying generic circuits and universally quantified properties but they require explicit user guidance, which makes them quite uninteresting for industry usage. As a first step to overcome these issues, this paper p...
By S. Shiraz , O. Hasan