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Virtual Distinguished Lecturer Program

Due to pandemic and travel restrictions, the traditional format of the Distinguished Lecturer Program (DLP) is not possible.The Virtual Distinguished Lecturer Program (VDLP) allows us to continue to serve the CEDA participants and the electronic design automation community the opportunity to hear from our respected Distinguished Lecturers.

The virtual series will feature one lecturer a month. Registration is free for all webinars. If you are unable to attend the "live" virtual events, the presentations will be available on our Presentation Library and the CEDA YouTube channel after the event.

Date/Time (EST) Title Distinguished Lecturer Registration Recordings
THUR. APR 22, 2021
10:00AM-11:00 AM  ET

Distributed Visual Analytics

Vijaykrishnan Narayanan

🌐 Zoom

📺 Watch
THUR. May 20, 2021
11:00AM-12:00 PM  ET
An EDA Researcher’s Journey Into AI Yiran Chen 🌐 Zoom 📺 Watch

THUR. JUNE 24, 2021
11:00AM-12:00 PM  ET

Closing the Virtuous Cycle of AI for IC and IC for AI David Pan 🌐 Zoom  
THUR. JULY 15, 2021
11:00AM-12:00 PM  ET
Predictive Analytics in Machine Learning for VLSI Circuits Rajiv Joshi 🌐 Zoom  
THUR. AUG. 19, 2021
11:00AM-12:00 PM  ET
TBD Sharon Hu 🌐 Zoom  
THUR. SEPT. 23, 2021
11:00AM-12:00 PM  ET
Automating Analog Layout in the 21st Century Sachin Sapatnekar 🌐 Zoom  
OCTOBER 2021 TBD        

THUR. NOV. 18, 2021
11:00AM-12:00 PM  ET

TBD Yier Jin 🌐 Zoom  
DECEMBER 2021 TBD        

DL Program Manager

Mehdi Tahoori

Karlsruhe Institute of Technology
8 (Africa, Europe, Middle East)

Virtual DL Talks

Vijaykrishnan Narayanan

Distinguished Lecturer 2018 - 2021

Distributed Visual Analytics

April 22, 2021 at 10:00 AM ET

Visual content continues to be on the rise.  Increasingly, visual analytics are part of computational pipelines supporting latency-sensitive and interactive applications such as situational awareness, which combine content dynamically aggregated from sensors and end-user devices. The talk will highlight assistive visual systems for persons with visual impairments and a pollinator-tracking system as examples of such end uses. Using these application contexts, the design space of  these distributed sensors will be explored with focus on communication costs.  Next, the talk will focus on Video query processing that is evolving from applications that query pre-extracted metadata using traditional query processing techniques to applications that directly analyze geometry, semantics, and content in the video bitstream. This talk will showcase ongoing efforts in system level design. Finally,  we will show some new opportunities with the shift from 2D to 3D sensors. The talk leverages effort from collaborators from the SRC JUMP Visual Analytics team and the NSF Expeditions in Computing Visual Cortex on Silicon program.


Yiran Chen

Distinguished Lecturer 2018 - 2021

An EDA Researcher’s Journey Into AI

may 20, 2021 at 11:00 AM ET

Abstract: Artificial Intelligence (A) ubiquitously impacts almost all research societies including electronic design automation (EDA). Many scholars with mathematic and modeling backgrounds have shifted their focuses onto applying AI technologies to their research or directly working on AI problems. As a researcher with a Ph.D. training of EDA and circuit designs, I started my AI-relevant research since late 2000s, i.e., neuromorphic computing that implements hardware to accelerate computation of biologically plausible learning models. In this talk, I will review the development process of my research from neuromorphic computing to a broader scope of AI, including machine learning accelerator designs, neural network quantization and pruning, neural architectural search, federated learning, and neural network robustness, privacy, security, etc., and how I benefit from my EDA background.


David Pan

Distinguished Lecturer 2019 - 2021

Closing the Virtuous Cycle of AI for IC and IC for AI

June 24, 2021 at 11:00 AM ET

The recent artificial intelligence (AI) boom has been primarily driven by three confluence forces: algorithms, data, and computing power enabled by modern integrated circuits (ICs), including specialized AI accelerators. This talk will present a closed-loop perspective for synergistic AI and agile IC design with two main themes, AI for IC and IC for AI. As semiconductor technology enters the era of extreme scaling, IC design and manufacturing complexities become extremely high. More intelligent and agile IC design technologies are needed than ever to optimize performance, power, manufacturability, design cost, etc., and deliver equivalent scaling to Moore’s Law. This talk will present some recent results leveraging modern AI and machine learning advancement with domain-specific customizations for agile IC design and manufacturing closure. Meanwhile, customized ICs, including those with beyond-CMOS technologies, can drastically improve AI performance and energy efficiency by orders of magnitude. I will present some recent results on hardware/software co-design for high performance and energy-efficient optical neural networks. Closing the virtuous cycle between AI and IC holds great potential to advance the state-of-the-art of each other significantly.


Rajiv Joshi

Distinguished Lecturer 2019 - 2021

Predictive Analytics in Machine Learning for VLSI Circuits

July 15, 2021 at 11:00 AM ET

As semiconductor technology enters the sub-14nm era, geometry, process, voltage and temperature (PVT) variability in devices can affect the performance, functionality, and power of circuits, especially in new Artificial Intelligent (AI) accelerators. This is where predictive failure analytics is extremely critical. It can identify the failure issues related to logic and memory circuits and drive the circuits in energy efficient area.

This talk describes how key statistical techniques and new algorithms can be effectively used to analyze and build robust circuits.  These algorithms can be used to analyze decoders, latches, and volatile as well as non-volatile memories. In addition, how these methodologies can be extended to “reliability prediction” and “hardware corroboration” is demonstrated. Logistic regression-based machine learning techniques are employed for modeling the circuit response and speeding up the importance sample points simulations. To avoid overfitting, a cross-validation based regularization framework for ordered feature selection is demonstrated.  

Also, techniques to generate accurate parasitic capacitance modeling along with PVT variations for sub-22nm technologies and their incorporation into a physics-based statistical analysis methodology for accurate Vmin analysis are described. In addition, extension of these techniques based on machine learning e.g KNN is highlighted. Finally, the talk summarizes important issues in this field.


Xiaobo Sharon Hu

Distinguished Lecturer 2018 - 2021


august 19, 2021 at 11:00 AM ET

Abstract: TBD


Sachin Sapatnekar

Distinguished Lecturer 2018 - 2021

Automating Analog Layout in the 21st Century

SEPTEMBER 23, 2021 at 11:00 AM ET

Abstract: TBD


Yier Jin

Distinguished Lecturer 2019 - 2021


november 18, 2021 at 11:00 AM ET

Abstract: TBD

About CEDA's DL Program

The IEEE CEDA Distinguished Lecturer Program promotes the field of electronic design automation to the scientific community and the public at large. The goal of the program is to increase awareness about topics relevant to CEDA by creating a pool of subject matter experts and scholars to present to IEEE and CEDA Chapters, Sections and other venues such as universities and companies.