To recognize an individual who has made substantial contributions to the area of Electronic Design Automation in the early stages of his or her career.
Award/Recognition Menu
1000 USD and a plaque for up to two recipients annually. Travel reimbursement is not provided.
The IEEE Council on Electronic Design Automation (CEDA).
The award will be presented at the ACM/IEEE International Conference on Computer-Aided Design (ICCAD).
The IEEE CEDA Ernest S. Kuh Early Career Award honors an individual who has made innovative and substantial technical contributions to the area of Electronic Design Automation in the early stages of his or her career.
In the spring of 2015, the IEEE CEDA Board of Governors voted unanimously to approve the proposal to rename the IEEE CEDA Early Career Award to the "IEEE CEDA Ernest S. Kuh Early Career Award" in honor of the late Prof. Ernest S. Kuh, who made pioneering contributions to circuit theory, EDA, and engineering education.
About Ernest S. Kuh
Ernest S. Kuh was a professor emeritus and dean of the UC Berkeley College of Engineering from 1973 to 1980. Professor Kuh passed away on 27 June 2015.
Ernest S. Kuh joined the Berkeley faculty in 1956 and made pioneering contributions to circuit theory, EDA of integrated circuits, and engineering education.
Ernest S. Kuh mentored and supervised several generations of graduate students who today occupy leadership positions in academia and industry.
Ernest S. Kuh was a Fellow of IEEE and AAAS. He received numerous awards and honors, including the ASEE Lamme Medal, IEEE Centennial Medal, IEEE Education Medal, IEEE Circuits and Systems Society Award, IEEE Millennium Medal, the 1996 C&C Prize, and the 1998 EDAC/IEEE CEDA Phil Kaufman Award.
The award shall be based on contributions to the field of EDA. Contributions will be measured based on technical merit and creativity in performing research and will be assessed based on the published record of the individual and the references accompanying the nomination.
The award is intended to be equally available to contributors from academic and industrial institutions.
The Award Committee will judge nominees according to their contributions to the field of EDA. Contributions will be measured based on technical merit and creativity in performing research and will be assessed based on the published record of the individual and the references accompanying the nomination. The award is intended to be equally available to contributors from academic and industrial institutions. Some of the specific criteria used will be: current and potential impact of the individual's contributions, as well as contributions to the profession at large
Full members of the IEEE at any level (regular, senior, or fellow grades) whose highest educational degree has been awarded within 8 years of the date of nomination.
2025
For contributions to the domain of hardware-software co-design of neuromorphic computing systems
2024
For outstanding contributions to design methodologies, optimization, and automation targeting emerging integrated photonic systems-on-chip.
2023
For outstanding contributions to high-assurance design of cyber-physical systems using contract-based design methodology.
2022
For contributions to machine learning in physical design and design for manufacturability.
2021
For contributions towards secure and trustworthy integrated circuits.
For contributions towards fundamental stochastic computation methods for circuit simulation and testing and beyond.
2020
For contributions to hardware security.
2019
For contributions to Electronic Design Automation targeting emerging logic and memory technologies.
2018
For contributions to network-on-chip interconnects for multi-core cyber-physical systems.
2017
For sustained and outstanding contributions to energy-efficient system-level design, including temperature-aware design and management, 3D-stacked system design, and management of large-scale computing systems.
2016
For contributions to energy-efficient design of reliable embedded and cyber-physical systems.
2015
For outstanding contributions to algorithms, methodologies, and successful commercialization of high-level synthesis tools for FPGAs.
2014
For her outstanding contributions to design verification, including automatic invariant generation, coverage analysis, timing verification, and analog verification.
2013
For sustained and outstanding contributions to design methods and tools for multi-processor systems-on-chip (MPSoC), particularly for work on thermal-aware design, low-power architectures and on-chip interconnects synthesis.
For essential and outstanding contributions to algorithms, methodologies, and software for interconnect optimization, physical synthesis, parasitic extraction, testing, and simulation.
2012
For seminal contributions to system-level design, including latency-insensitive design, on-chip communications synthesis and compositional design-space exploration.
2011
For exceptional contributions in the area of hardware verification, particularly for work on semi-formal verification, runtime and post-silicon verification, and correctness-constrained execution.
2010
For contribution to electromagnetic field analysis, parasitic variation-aware extraction and automated parameterized linear and non-linear stable model reduction.
2009
For outstanding contributions to algorithms, methodologies and software for the physical design of integrated circuits.