Subhasish Mitra

Subhasish Mitra

Affiliation
Stanford University
IEEE Region
Region 06 (Western U.S.)
(
Country
USA
)

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Subhasish Mitra is currently a Professor of Electrical Engineering and Computer Science at Stanford University, Stanford, CA, USA, where he directs the Stanford Robust Systems Group and co-leads the computation focus area of the Stanford SystemX Alliance. He is also a Faculty Member with the Neurosciences Institute, Stanford University. He holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI, Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation, Santa Clara, CA, USA. His current research interests include broadly across robust computing, nanosystems, VLSI design, validation, test, and electronic design automation, and neurosciences. He along with his students and collaborators demonstrated the first carbon nanotube computer and the first 3-D nanosystem with computation immersed in data storage. These demonstrations received widespread recognitions (cover of Nature, Research Highlight to the U.S. Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, The Economist, Electronic Engineering Times, IEEE Spectrum, MIT Technology Review, National Public Radio, The New York Times, Scientific American, Time, The Wall Street Journal, The Washington Post, and numerous others worldwide). His earlier work on X-Compact test compression has been a key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial electronic design automation tools. He is a Fellow of the Association for Computing Machinery (ACM) and IEEE. He received the Association for Computing Machinery Special Interest Group on Design Automation/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test-of-time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel's highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He along with his students published several award-winning papers at major venues, including the ACM/IEEE Design Automation Conference, the IEEE International Solid-State Circuits Conference, the ACM/IEEE International Conference on Computer-Aided Design, the IEEE International Test Conference, the IEEE Transactions on Computer-Aided Design, the IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. He was honored several times by graduating seniors for being important to them during their time at Stanford. He has served on the Defense Advanced Research Projects Agency's Information Science and Technology Board as an Invited Member.

IEEE CEDA Position History:
  • Present   Editor-at-Large Board (Transactions on Computer Aided Design of Integrated Circuits & Systems Editoral Board)
  • Present   Member (Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award Committee)
  • 2024-Present   Member (Fellows Evaluation Committee)
  • 2024-Present   Assistant Vice President Strategy (Executive Committee)
  • 2024-Present   Vice Chair (Cohort Fellow Evaluating Committee)
  • 2024-Present   Member (Strategy Committee)
  • 2022-2023   Assistant VP Publications (Executive Committee)
  • 2022-2023   Member (Publications Committee )
  • 2021-2022   Member (Fellows Evaluation Committee)
  • 2020-2021   Chair (A. Richard Newton Technical Impact Award Committee)
  • 2020-2021   Member (A. Richard Newton Technical Impact Award Committee)
  • 2018-2021   Vice President Awards (Executive Committee)
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