Vivek Chickermane

Biography

Vivek Chickermane is a Distinguished Engineer at Cadence Design Systems where he is also a Senior Group Director for R&D in the Modus DFT Software group which is a part of Cadence’s Digital Systems Group. His professional responsibilities include design and productization of in-system DFT features that are used in high quality and safety-critical applications. He has been involved in the frontlines of productizing key DFT features such as OPMISR Compression technology in 2001, IEEE 1149.6 (AC-JTAG) in 2004, IEEE 1500 Core Test Wrapper synthesis in 2005, development of the first EDA Common Power Format (CPF) in 2008 which could be used by all tools in an RTL to GDS2 including power-aware test. His team’s contributions to power-aware test led to a “Best In Test Award” in 2008 from Test and Measurement World Magazine. More recently he and his team have productized low-pin count compression, 3D IC DFT, Hierarchical Test Compression using pattern porting, IEEE 1687 (iJTAG) and physically-aware 2D Compression to reduce the cost of test. Prior to Cadence, Dr. Chickermane was at IBM’s Microelectronics Division where he led the development of the first DFT Synthesis tool in their BooleDozer Synthesis tool which was used in the front-end of their vector-less ASIC sign-off flow. Dr Chickermane has published more than 80 technical refereed technical articles and papers and is also a co-inventor of more than 40 US patents awarded or pending. He serves on several IEEE conference and standards committees and is currently an Associate Editor of IEEE Design & Test. He received his B.Tech in Electrical Engineering from Indian Institute of Technology, New Delhi and his M.S and Ph.D degrees in Computer Engineering from the Univ. of Illinois at Urbana-Champaign.