William Hung

William Hung headshot

William Hung

IEEE Region: 5 (Southwestern U.S.)


William N. N. Hung started his career at Intel in 1997 applying formal methods to the design and verification process of leading-edge microprocessors. In 2004, he left Intel to join Synplicity and worked on FPGA synthesis. In 2007, he joined Synopsys to work on emulation, prototyping, and constraint-based verification. Since January 2019, he has been working at Cadence as a Distinguished Engineer to work on leading-edge EDA technologies.

William is serving as an Associate Editor of IEEE Transactions on CAD and IEEE Transactions on Circuits and Systems II. He served on the Technical Program Committee (TPC) of several conferences including DAC (Design Automation Conference), ICCAD, DATE, ICCD, CAV, FMCAD, WCCI, CEC, etc. He was the Chair of the Quantum Computing Task Force of the IEEE Computational Intelligence Society, and he also served as Chair of High-level, Behavioral and Logic Synthesis Track in the ICCAD TPC and as Co-Chair of the Logic and Circuit Track in the ICCD TPC. He has 20+ years of industrial R&D experience, 80+ papers published, and he is the inventor of numerous patents. He gave invited talks to CAV 2015 and ISPD 2018. 

Positions & Affiliations

Cadence Design Systems
United States