Yiran Chen

Fast growth of the computation cost associated with training and testing of deep neural networks (DNNs) inspired various acceleration techniques. Reducing topological complexity and simplifying data representation of neural networks are two approaches that popularly adopted in deep learning society: many connections in DNNs can be pruned and the precision of synaptic weights can be reduced, respectively, incurring no or minimal impact on inference accuracy. However, the practical impacts of hardware design are often ignored in these algorithm-level techniques, such as the increase of the random accesses to memory hierarchy and the constraints of memory capacity. On the other side, the limited understanding about the computational needs at algorithm level may lead to unrealistic assumptions during the hardware designs. In this talk, we will discuss this mismatch and show how we can solve it through an interactive design practice across both software and hardware levels.

The goal of this seminar is to give an overview of working mechanisms of several emerging nonvolatile memory technologies, i.e., spintronic memory, phase change memory, resistive memory, and ferroelectric memory, etc., and their applications in next-generation storage and computing systems. The presenter will first introduce electrical properties of these memory technologies that make them unique from the mainstream memory technologies. Next, the presenter will discuss some typical circuit designs targeting the concerned applications, i.e., TCAM, on-chip cache, standalone memory, and storage class memory. The presenter will then illustrate the new requirements of next-generation storage and computing systems and their solutions by leveraging the unique properties of emerging memory technologies, such as fast access time, nonvolatility, high integration density, and good CMOS process compatibility. At the end of this talk, the presenter will list some common circuit design challenges of these emerging memory technologies, e.g., high write cost, asymmetric programming performance at 1 and 0, and the approaches that can alleviate these challenges at circuit design and computer architecture levels.

Although Deep Neural Networks (DNN) are ubiquitously utilized in many applications, it is generally difficult to deploy DNNs on resource-constrained devices, e.g., mobile platforms. In practical use, both testing (inference) phase and sophisticated training (learning) phase are required, calling for efficient testing and training methods with higher accuracy and shorter converging time. In this tutorial, we first introduce DNNs from a historical perspective and then present some representative techniques to reduce the computation cost of DNN, including network pruning, model compression, low precision design etc. In rial, we will show some examples to perform and optimize the training and testing of DNN on distributed mobile systems.

• Introduction to neural networks 

• History, structure, algorithms, and software 

This tutorial will provide attendees a holistic and historical view about technology evolutions of emerging nonvolatile memory in devices, circuit design, and architectural applications. The presenter will first briefly describe the basic physics of several important emerging nonvolatile memory technologies – magnetic memory, resistive memory, phase change memory, and ferroelectric memory, as well as some common device engineering tradeoffs. After that, the presenter will introduce several typical emerging memory cell designs that maximize the advantages of these emerging storage devices, e.g., non-volatility, multi-level cell, and small footprint, and alleviate device drawbacks like high programming current/voltage etc. The focus will be given to the circuit design development following the advance in device engineering in last two decades from a device-circuit co-design perspective. The presenter will then go through the computer architectures that have built their memory hierarchy with the emerging non-volatile memory technologies for various concerns on power, performance, and reliability. Again, some solutions that mitigate the drawbacks of emerging memories and significantly enhance the computing systems’ efficiency and robustness will be discussed in details. Finally, the presenter will give the prospect of new applications of emerging nonvolatile memory technologies in future computing systems like neuromorphic computing etc.

• Device physics and basic working mechanisms 
• Device engineering for various applications 
• Memory cell design tradeoffs between area, power, performance, and reliability 
• Special memory cell designs to overcome the device drawbacks and multi-level cells 
• Memory structures for fast access time and high endurance 
• On-chip memory hierarchy: performance-driven designs 
• Off-chip memory hierarchy: density-driven designs 
• Applications in persistency retaining and neuromorphic computing