Country
USA
Paper
An efficient graph representation for arithmetic circuit verification
Volume Number:
20
Issue Number:
12
Pages:
Starting page
1443
Ending page
1454
Publication Date:
Publication Date
1 December 2001
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Abstract
In this paper, we propose a new data structure called multiplicative power hybrid decision diagrams (*PHDDs) to provide a compact representation for functions that map Boolean vectors into integer or floating-point (FP) values. The size of the graph to represent the IEEE FP encoding is linear with the word size. The complexity of FP multiplication grows linearly with the word size. The complexity of FP addition grows exponentially with the size of the exponent part, but linearly with the size of the mantissa part. We applied *PHDDs to verify integer multipliers and FP multipliers before the rounding stage, based on a hierarchical verification approach. For integer multipliers, our results are at least six times faster than binary moment diagrams. Previous attempts at verifying FP multipliers required manual intervention, but we verified FP multipliers before the rounding stage automatically.
