Paper

Energy-Efficient, Low-Latency Realization of Neural Networks through Boolean Logic Minimization

Publication Date:
Publication Date
April 2024
Author(s)
M. Nazemi, G. Pasandi and M. Pedram

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Abstract

Deep neural networks have been successfully deployed in a wide variety of applications including computer vision and speech recognition. To cope with computational and storage complexity of these models, this paper presents a training method that enables a radically different approach for realization of deep neural networks through Boolean logic minimization. The aforementioned realization completely removes the energy-hungry step of accessing memory for obtaining model parameters, consumes about two orders of magnitude fewer computing resources compared to realizations that use floating-point operations, and has a substantially lower latency.