Title
Patrick Schaumont
Country
USA
Affiliation
Worcester Polytechnic Institute
Side-channel leakage certification on silicon prototype ICs is expensive and a significant burden on the streamlined design process. This panel gathers experts from industry, government, academia and the CAD vendor world, to discuss how CAD tools can address the side-channel leakage problem pre-silicon. The panel will discuss requirements and feasibility of side-channel leakage assessment, design under side-channel leakage constraints, and side-channel leakage design sign-off in deep sub-micron technology nodes.
Organizers: Swarup Bhunia, Gang Qu, Yier Jin, Tsung-Yi Ho