Ramesh Nair has over 10 years of experience in the semiconductor industry. Ramesh works as an EDA Tools Engineering Manager at Intel Corporation in Folsom, California. At Intel, he manages a team that develops tools, flows and methodology for next generation core CPU and SoC designs.  Ramesh’s areas of technical interest include Electronic Design Automation, Static Timing Analysis and Low Power Circuit Design. He is a recipient of multiple Intel Organizational and Department awards and the 2014 Design Automation Conference (DAC) Young Research Fellowship. Ramesh currently serves on the Board of Governors of the IEEE Council on Electronic Design Automation (CEDA). He holds a master’s degree in Computer Engineering from University of Cincinnati.

Ramesh is an IEEE Senior Member with volunteering and leadership experience at the local and global levels. Ramesh is currently a member-at-Large of the IEEE Awards Board and a past member of the IEEE-USA Board of Directors and IEEE MGA Awards & Recognition Committee. He is also a member of the IEEE Awards Board Presentation & Publicity Committee (P&P). Ramesh is a recipient of the 2018 IEEE MGA Achievement Award, 2017 IEEE MGA Young Professionals Achievement Award and 2020 & 2017 IEEE Region 6 Director’s Recognition Award. He is an advocate and volunteer for local STEM outreach initiatives. He is also a professional member of the Eta Chapter of IEEE-HKN.