IEEE Design&Test: Call for Papers

IEEE Design&Test is soliciting submissions for its Special Issue on LLM-aided Hardware Design, Verification, and Test. 

This special issue is dedicated to LLM-based hardware design, verification, and test. Topics of interest include (but are not limited to):

• LLM-based digital circuit design
• LLM-based layout optimization
• LLM-based analog/mixed-signal/RF circuit design 
• LLM-based hardware security
• LLM-based design verification 
• Applications of LLM for hardware testing
• LLM-based assertion generation 
• LLM-based silicon lifecycle management
• LLM-based synthesis

Submission deadline: 1 April 2025

For more information, please visit: https://ieee-ceda.org/publication/design-test#documents