Strategies for Evaluating the Impact of Emerging Memory Technologies at the Application-Level

This talk will consider systematic ways to convolve application-level benchmarking efforts (which frequently leverage analysis of peripheral circuit overheads) with quantitative analysis of emerging memory device key performance indicators (KPIs) that are also of interest to industry (i.e., device self-consistency/target cell repeatability; device-to-device repeatability, targeting small 6 sigma; device retention; device endurance; read disturb; large resistance differentials).  We show how array-level analysis (e.g., of peripheral overheads) can provide quantitative estimates of figures of merit (FoM) such as {array, application}-level area, latency, and energy, as well as qualitative insight as to the impact on memory KPIs.  With physics-based device models and/or experimental measurements, we can further quantify both memory KPIs, as well as additional application-level FoM such as accuracy.   We present our approach in this talk primarily in the context of ferroelectric devices, but will comment on other memory technologies as well.