Sachin Sapatnekar University of Minnesota United States 4 (Central U.S.) Email Website 2018 2021 Talk(s): Spintronics: From Devices to Circuits to Systems Spintronics: From Devices to Circuits to Systems × Spintronics technology provides an exciting platform for implementing computational structures, and recent work has demonstrated the potential for leveraging its nonvolatility properties to build energy-efficiency systems. This talk presents a view of the state of the art in this field, as well as a view of cutting-edge research directions. We will present results from our collaborative efforts involving physicists, material scientists, circuit designers, and architects, which have led to the development of novel device structures, circuits, and memory arrays. Together, these help construct viable pathways for building spin-based structures for computation, memory, and in-memory computation, including for AI applications. Spin-based memories are nonvolatile and are conventionally based on arrays of magnetic tunneling junctions (MTJs). The talk will first show the current state of technology for building spin-based memories, and then present directions for next-generation improvements in spintronic memory technologies. We will then present spin-based structures that have also been shown to be highly efficient for logic applications in specific scenarios, such as those that require nonvolatility or are used for error resilient applications. Finally, we will show methods for building spin-based compute-in-memory structures that are greatly advantageous for data-intensive applications, and demonstrate the efficiencies that can be achieved by this model for a neuromorphic application. Reliability, Error-resilience, and Approximation in Integrated Systems Reliability, Error-resilience, and Approximation in Integrated Systems × As CMOS technology matures, the problem of building fully reliable circuits has become more challenging, as a variety of mechanisms that perturb system performance have come into play. These range from ”one-time” drifts due to process variations, which shift circuit performance, to ”run-time” shifts caused by aging mechanisms, which cause degradations and/or failures in devices and interconnects. Developing design mechanisms that model and overcome these shifts requires an understanding from the device level, circuit level, system level, and application level. At the device level, methods that comprehend performance shifts due to statistical as well as deterministic variations due to process and aging are key. At the circuit level, these must be factored into statistical and intelligent corner-based performance analysis approaches, as well as mechanisms that enable post-silicon compensation. At the system level, compensation and redundancy schemes must be utilized to ensure that the system operates at the desired performance, within a specified power budget. An equally important consideration arises from application-level requirements. While some mission-critical applications, or segments of applications, require absolute accuracy, many emerging applications (e.g., signal filtering, image/video operations, neuromorphic applications) show a good deal of error-resilience, implying that absolute accuracy is not essential. In these scenarios, it is possible to selectively ignore ”accidental” errors due to process and aging, or even introduce deliberate errors in hardware to build approximate systems that provide just enough accuracy for the application. Using a case study approach, it will be shown how application-level considerations will be used to approximate systems that optimize power and performance within a specified error budget.
