Vivek De

Many-core system-on-chip (SoC) architecture and design challenges and opportunities spanning edge devices to cloud computing systems inscaled CMOS process are presented. Key techniques for robust and variation-tolerant logic, embedded memory arrays and on-die interconnectfabrics are discussed. Fine-grain multi-voltage design and power management techniques, featuring integrated voltage regulators for widedynamic voltage-frequency operating range and fl exible platform power control across multi-threaded high-throughput near-threshold voltage(NTV) to single-threaded burst performance modes, are elucidated. Smart variation-aware workload mapping, runtime self-adaptation and errordetection and recovery schemes to mitigate impacts of process-voltage-temperature (PVT) variations and aging, and achieve maximumperformance under stringent thermal and energy constraints, are presented. Latest advances in design and process/package for realization ofmonolithic and heterogeneous 2D/3D-integrated compact, effi cient, low supply noise, fi ne-grain, high-bandwidth and fast-response powerconverters and voltage regulators, essential for implementing intelligent system-level power management and adaptation schemes acrosshardware and software, are also highlighted. Real SoC examples are used to demonstrate leading-edge practical systems.

SoC design challenges and opportunities for smart and secure cyberphysical systems in the world of Internet-of-Things (IoT) are presented,focusing on two distinct areas: (1) how to deliver uncompromising performance and user experience while minimizing energy consumption, and(2) how to provide cryptographic-quality “roots of trust” in silicon and resistance to physical side channel attacks with minimal overhead. SoCdesigns that span a wide range of performance and power across diverse platforms and workloads, and achieve robust near-threshold-voltage(NTV) operation in nanoscale CMOS, are discussed. Techniques to overcome the challenges posed by device parameter variations, supplynoises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations are presented. TrueRandom Number Generator (TRNG) and Physically Unclonable Function (PUF) circuits, the two critical silicon building blocks for generatingdynamic and static entropy for encryption keys and digital fi ngerprints, respectively, are discussed. Power and electromagnetic physical side-channel-attack detection and mitigation techniques for enabling robust hardware security are also presented.