Variation-Tolerant and Error-Resilient Many-Core SoCs with Fine-Grain Power Management

Many-core system-on-chip (SoC) architecture and design challenges and opportunities spanning edge devices to cloud computing systems in scaled CMOS process are presented. Key techniques for robust and variation-tolerant logic, embedded memory arrays and on-die interconnect fabrics are discussed. Fine-grain multi-voltage design and power management techniques, featuring integrated voltage regulators for wide dynamic voltage-frequency operating range and flexible platform power control across multi-threaded high-throughput near-threshold voltage(NTV) to single-threaded burst performance modes, are elucidated. Smart variation-aware workload mapping, runtime self-adaptation and error detection and recovery schemes to mitigate impacts of process-voltage-temperature (PVT) variations and aging, and achieve maximum performance under stringent thermal and energy constraints, are presented. Latest advances in design and process/package for realization of monolithic and heterogeneous 2D/3D-integrated compact, efficient, low supply noise, fine-grain, high-bandwidth and fast-response power converters and voltage regulators, essential for implementing intelligent system-level power management and adaptation schemes across hardware and software, are also highlighted. Real SoC examples are used to demonstrate leading-edge practical systems.