FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications – A 7-year Experience

With the increasing complexity of today’s MPSoC applications, extremely high performance has become the main requirement. However, high performances do not only mean high speed but also low power. However, most of the time, ultra-low power architectures cannot reach high speed and conversely, at high speed, a lot of power is consumed. Designing Ultra Wide Voltage Range (UWVR) systems at the nanometer regime is a way to achieve high energy efficiency but introduces many challenges due to the emphasis of parasitic phenomenon effects driven by the scaling of bulk MOSFETs, making circuits more sensitive to the manufacturing process fluctuations and less energy efficient. How to improve the trade-off between leakage, variability and speed at low-voltage? Obviously, the trend is to use thin film devices. Undoped thin-film planar FDSOI devices are being investigated in this presentation as an alternative to bulk devices in 28nm node and beyond. This talk will highlight the development of an UWVR multi-VT design platform in FDSOI planar technology on Ultra Thin Body and Box (UTBB) for the 28nm node. The use of an efficient Body Biasing (BB) shows an extremely efficient performance tuning for high-energy efficiency. We will also explore FDSOI benefits for new ULP applications and IoT perspectives.