Machine Learning Assisted Sign-Off: Cost and Effect

Relentless scaling in semiconductors and the growing complexity of System-on-Chip (SoC) integration have presented various challenges in design sign-off, from problem size to formulation complexity. On the other hand, the success of Machine Learning (ML), particularly deep learning, has sparked widespread interest in ML-powered design automation. A notable example is Google's Placer, which uses deep reinforcement learning and has garnered much attention in academia and industry. It's important to note that unlike many computer vision problems, sign-off problems already have a well-established mathematical and physical law-based system. This raises questions about the scope and effectiveness of ML techniques in sign-off Electronic Design Automation (EDA). Moreover, sign-off verification requires high accuracy and, in some cases, exact solutions, while ML techniques are known to result in unpredictable accuracy loss. This talk will start with a comprehensive overview of the directions in which ML will improve the cost and efficiency of sign-off. It will then delve into the successful applications of ML in power and timing sign-off, as well as its deployment in industrial practices to speed up sign-off convergence. Finally, the talk will summarize the lessons we learned during this trip of bringing ML to sign-off problems.