Trustworthy AI: The role of the Hardware

In the recent years, AI algorithms became so accurate that started to surpass human being in a wide range of tasks and are now currently used in applications that would be considered science-fiction only 10 years ago. However, everything as a cost and, for AI, it corresponds to the tremendous requirements in terms of computational power that driven the development of specialized hardware architectures (i.e., hardware accelerator) for DL workloads. One of the most popular hard- ware accelerator is the Systolic Array (SA) architecture, which is suitable to run inferences with low energy, low latency and high throughput. In particular, there exists virtually infinite types of SA in terms of dataflow depending on the kernel they have to run. If from one hand SA dataflow has been widely studied to improve energy efficiency and performance, the impact on the resilience to hardware faults has been neglected. Hardware faults can indeed jeopardize the execution of DL kernels leading to miss- classification and eventually to dramatic impacts when DL are used in safety-critical applications, such as autonomous driving. This talk will discusses the main consequences on the choice of a given hardware architecture to achieve by design Trustworthiness.