Board of Governors | IEEE Council on Electronic Design Automation

President

Yao-Wen Chang

National Taiwan University

Taiwan

10 (Asia and Pacific)

Yao-Wen Chang

10 (Asia and Pacific)

Biography

Yao-Wen Chang received the B.S. degree in Computer Science and Information Engineering from National Taiwan University (NTU) in 1988, and the M.S. and Ph.D. degrees in Computer Science from the University of Texas at Austin in 1993 and 1996, respectively.

He is an IEEE Fellow and the IEEE CEDA President-elect (2018-2019) and will be the President (2020-2021). Currently, he is Deputy Vice President for Academic Affairs (副教務長), NTU, Director of the Center for Teaching and Learning Development, NTU, Director of the Digital Learning Center, NTU, and Distinguished Professor of the Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, NTU, Taipei, Taiwan. He was an associate dean of the College of Electrical Engineering and Computer Science from 2012-2016 and the director of the Graduate Institute of Electronics Engineering of NTU from 2010 to 2013. Dr. Chang was a visiting professor of Waseda University (早稻田大學) in Japan from 2005 to 2010 and a visiting scholar of the Computer Science and Artificial Intelligence Laboratory (CSAIL) of Massachusetts Institute of Technology (MIT) in 2014. He was a 2nd Lieutenant during his compulsory military service from 1988 to 1990, a Research Assistant in the Institute of Information Science, Academia Sinica, Taiwan from 1990 to 1991, and a Teaching/Research Assistant in the Department of Computer Sciences, the University of Texas at Austin from 1992 to 1996. In the summers of 1994 and 1995, he was a Research Staff Member in the VLSI Design Group at IBM T. J. Watson Research Center, Yorktown Heights, New York and a teaching assistant in the VLSI Design Automation Group at IBM, Austin, Texas, respectively. From 1996 to 2001, he was an Associate Professor in the Department of Computer and Information Science, National Chiao Tung University, Hsinchu, Taiwan. His current research interests include electronic design automation (with emphases on physical design and manufacturability) and combinatorial optimization. He has been working very closely with the semiconductor industry on projects and has co-authored a book on routing (Springer, 2007), co-edited a book on electronic design automation (Morgan Kaufmann, 2009; 934 pages), and published about 300 ACM/IEEE conference/journal papers in these areas, including a few highly cited works on floorplanning, placement, routing, manufacturability, and FPGA. His NTUplace3 placer was the core engine of the popular Digital Custom Placer (in Laker) of Synopsys. His NTUplace4 is the core engine of Maxeda’s MaxPlacer, a 3-time champion placer (DAC’12, ICCAD’13, and ISPD’15 Placement Contests). He was ranked #1 worldwide among 40K+ researchers by the Microsoft Academic Search Database for Recent Five-Year Citations in the Hardware and Architecture Domain during November 2011 -- March 2012.

Dr. Chang received four awards at the 50th ACM/IEEE DAC in 2013 for the 1st Most Papers in the 5th Decade (34 DAC papers in the 5th decade; #1 worldwide), Most Prolific Author (at least 6 papers) in a Single Year (2012, 2013), DAC Prolific Author Award (40 Club; now 62 papers, the #2 all-time DAC prolific author), one of the Longest Publication Streaks (15 years from 1999 to 2013; now 20 years, the #2 all-time DAC history). Dr. Chang is a 1st-place winner of six recent major ACM/IEEE EDA contests, including the 2015 ACM ISPD Blockage-Aware Detailed Routing-Driven Placement Contest, the 2013 IEEE CAD Contest @ ICCAD (Legalization and Detailed Placement), the 2012 ACM/IEEE DAC Routability-Driven Placement Contest, the 2012 ACM ISPD Discrete Gate Sizing Contest, the 2011 IEEE CEDA PATOS Timing Analysis Contest, and the 2009 ACM ISPD Clock Network Synthesis Contest. He has also received 18 other top-3 contest awards. He is a recipient of nine Best Paper Awards (2017 ACM/IEEE DAC, 2010 and 1995 IEEE ICCD, etc.), the 2007 IEEE/ACM ICCAD Professor Margarida Jacome Memorial Award, and two Best-in-Track Papers at the 2017 IEEE/ACM ICCAD. He has received 24 Best Paper Award Nominations from top international conferences, including DAC (7 times), ICCAD (4 times), and ISPD (5 times). He has received many research awards, such as the 2007, 2010, and 2013 Distinguished Research Awards (highest honor), Contract Research Fellow (2016--2018), and the 2004 Dr. Wu Ta You Memorial Award, all from Ministry of Science and Technology (formerly National Science Council) of Taiwan, and the 2010, 2012, and 2013 IBM Faculty Awards, the 2009 Distinguished EE Professor from the CIEE, the 2004 MXIC Young Chair Professorship from the MXIC Education Foundation, the 2017 TECO Award from the TECO Technology Foundation, and the 2015 MXIC Chair Professorship and the inaugural Research Achievement Award from National Taiwan University in 2004, distinguished teaching award in 2013 (2013-2018; highest honor for top 1% teachers)/excellent teaching awards (eight times in 2004, 2006, 2007, 2008, 2009, 2010, and 2011) from National Taiwan University, and excellent teaching award from National Chiao Tung University in 2000 (ranked #1 in the Department for this inaugural award).

Dr. Chang has served as an editor / associate editor of premier journals, including IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 2008 -- 2013, IEEE Transactions on VLSI Systems (TVLSI) 2015-now, IEEE Design & Test of Computers 2012 -- 2014 and 2016-now (as an interviews editor), IET Computers & Digital Techniques, the international Journal of Information Science and Engineering (JISE), etc. He has served as the steering committee/general/program chairs of ISPD, and general/program chairs of ICCAD, and program chair of ASP-DAC and FPT, and on the IEEE CEDA and ICCAD Executive Committees, the ASP-DAC Steering Committee, and the technical program committees of all major EDA conferences, including DAC, ICCAD, ISPD, ASP-DAC, DATE, ICCD, GLSVLSI, VLSI-DAT, FPL, FPT, APCCAS, etc. He was the CEDA Vice President of Technical Activities 2014-2015 and Conferences 2016-2017. He received the Outstanding Service Award from IEEE CEDA in 2015 and Recognition of Service Award from ACM in 2012. He has served as the chair of the EDA Consortium of the Ministry of Education of Taiwan and an independent board director of Genesys Logic, Inc, a technical consultant of MediaTek Inc., RealTek Semiconductor Corp., and Faraday Technology Inc., and a member of the Board Governors of the Taiwan IC Design Society, a Review Committee Member of the National Science Council, and a Principal Reviewer of the SBIR projects of the Ministry of Economics Affairs, Taiwan. He co-founded the Maxeda Technology, Inc. in 2015.

Affiliation(s)

National Taiwan University

Taiwan

President-Elect

Gi-Joon Nam

IBM Research

United States

1 (Northeastern U.S.)

Immediate Past President

David Atienza

École Polytechnique Fédérale de Lausanne

Switzerland

8 (Africa, Europe, Middle East)

David Atienza

8 (Africa, Europe, Middle East)

Biography

David Atienza Alonso received his MSc and PhD degrees in Computer Science and Engineering from Complutense Univ. of Madrid (UCM), Spain, and IMEC, Belgium, in 2001 and 2005. Currently, he is an associate professor of electrical and computer engineering, and head of the Embedded Systems Laboratory (ESL) at the Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland. His research interests include system-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) and low-power Internet-of-Things (IoT) systems, including new 2-D/3-D thermal-aware design for MPSoCs and many-core servers, ultra-low power system architectures for wireless body sensor nodes and edge computing, HW/SW reconfigurable systems, dynamic memory optimizations, and network-on-chip design. He is a co-author of more than 250 publications in peer-reviewed international journals and conferences, several book chapters, and eight U.S. patents in these fields. He has earned several best paper awards and he is (or has been) an Associate Editor of IEEE TC, IEEE D&T, IEEE T-TCAD, IEEE T-SUSC and Elsevier Integration. He was the Technical Programme Chair of IEEE/ACM DATE 2015 and General Programme Chair of IEEE/ACM DATE 2017. Dr. Atienza received the DAC Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He is an IEEE Fellow and an ACM Distinguished Member.

Affiliation(s)

École Polytechnique Fédérale de Lausanne

Switzerland

Secretary

Agnieszka Dubaj

Intel Corp.

United States

6 (Western U.S.)

Vice-President for Activities

Tsung-Yi Ho

National Tsing Hua University

Taiwan

10 (Asia and Pacific)

Tsung-Yi Ho

10 (Asia and Pacific)

Biography

Tsung-Yi Ho (SM’10) received the Ph.D. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2005. He is a Professor with the Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. He has presented ten tutorials and contributed 11 special sessions in ACM/IEEE conferences, all in design automation for microfluidic biochips. His research interests include design automation and test for microfluidic biochips and nanometer integrated circuits.

Dr. Ho is the recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science, the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, and the Hans Fischer Fellowship by the Institute of Advanced Study, Technical University of Munich. He was a recipient of the Best Paper Awards at the VLSI Test Symposium in 2013 and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2015. He served as a Distinguished Visitor of the IEEE Computer Society for 2013–2015, the Chair of the IEEE Computer Society Tainan Chapter for 2013–2015, and the Chair of the ACM SIGDA Taiwan Chapter for 2014–2015. He is currently an ACM Distinguished Speaker, a Distinguished Lecturer of the IEEE Circuits and Systems Society, and an Associate Editor for the ACM Journal on Emerging Technologies in Computing Systems, the ACM Transactions on Design Automation of Electronic Systems, the ACM Transactions on Embedded Computing Systems, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and the Technical Program Committees of major conferences, including the Design Automation Conference, the International Conference on Computer-Aided Design, the IEEE/ACM Design Automation and Test in Europe Conference, the Asia and South Pacific Design Automation Conference, the ACM/SIGDA International Symposium on Physical Design, and the International Conference on Computer Design.

Affiliation(s)

National Tsing Hua University

Taiwan

Vice-President for Awards

Subhasish Mitra

Stanford University

United States

6 (Western U.S.)

Subhasish Mitra

6 (Western U.S.)

Biography

Subhasish Mitra is currently a Professor of Electrical Engineering and Computer Science at Stanford University, Stanford, CA, USA, where he directs the Stanford Robust Systems Group and co-leads the computation focus area of the Stanford SystemX Alliance. He is also a Faculty Member with the Neurosciences Institute, Stanford University. He holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI, Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation, Santa Clara, CA, USA. His current research interests include broadly across robust computing, nanosystems, VLSI design, validation, test, and electronic design automation, and neurosciences. He along with his students and collaborators demonstrated the first carbon nanotube computer and the first 3-D nanosystem with computation immersed in data storage. These demonstrations received widespread recognitions (cover of Nature, Research Highlight to the U.S. Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, The Economist, Electronic Engineering Times, IEEE Spectrum, MIT Technology Review, National Public Radio, The New York Times, Scientific American, Time, The Wall Street Journal, The Washington Post, and numerous others worldwide). His earlier work on X-Compact test compression has been a key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial electronic design automation tools. He is a Fellow of the Association for Computing Machinery (ACM) and IEEE. He received the Association for Computing Machinery Special Interest Group on Design Automation/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test-of-time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel's highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He along with his students published several award-winning papers at major venues, including the ACM/IEEE Design Automation Conference, the IEEE International Solid-State Circuits Conference, the ACM/IEEE International Conference on Computer-Aided Design, the IEEE International Test Conference, the IEEE Transactions on Computer-Aided Design, the IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. He was honored several times by graduating seniors for being important to them during their time at Stanford. He has served on the Defense Advanced Research Projects Agency's Information Science and Technology Board as an Invited Member.

Affiliation(s)

Stanford University

United States

Vice-President for Conferences

Luca Fanucci

University of Pisa

Italy

8 (Africa, Europe, Middle East)

Vice-President for Finance

Cristiana Bolchini

Politecnico di Milano

Italy

8 (Africa, Europe, Middle East)

Vice-President for Initiatives

Ian O'Connor

École Centrale de Lyon

France

8 (Africa, Europe, Middle East)

Vice-President for Publications

L. Miguel Silveira

IST Técnico Lisboa

Portugal

8 (Africa, Europe, Middle East)

Vice-President for Publicity

Vasilis Pavlidis

University of Manchester

United Kingdom

8 (Africa, Europe, Middle East)

Vice-President for Standards

Dennis Brophy

Mentor, a Siemens Business

United States

6 (Western U.S.)

Vice-President for Strategy

Enrico Macii

Politecnico di Torino

Italy

8 (Africa, Europe, Middle East)

Young Professionals Coordinator

Qi Zhu

Northwestern University

United States

4 (Central U.S.)

Qi Zhu

4 (Central U.S.)

Biography

Dr. Qi Zhu is a tenured Associate Professor in the Department of Electrical and Computer Engineering (ECE) at Northwestern University. He was an Assistant Professor and later Associate Professor in the ECE Department at University of California, Riverside from 2011 to 2017, and a Research Scientist at the Strategic CAD Labs in Intel from 2008 to 2011. Dr. Zhu received a Ph.D. in EECS from University of California, Berkeley in 2008, and a B.E. in CS from Tsinghua University in 2003. His research interests include model-based design, synthesis and verification of cyber-physical systems (CPS) and Internet of Things, CPS security, embedded and real-time systems, connected and autonomous vehicles, energy-efficient buildings and infrastructures, and system-on-chip design. He received best paper awards at Design Automation Conference (DAC) 2006, DAC 2007, International Conference on Cyber-Physical Systems (ICCPS) 2013, and ACM Transactions on Design Automation of Electronic Systems (TODAES) 2016. He received the NSF CAREER award in 2016, and the IEEE TCCPS (Technical Committee on Cyber-Physical Systems) Early-Career Award in 2017. Dr. Zhu is an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IET Cyber-Physical Systems: Theory & Applications, and IEEE TCCPS Newsletter. He served as an Associate Editor for IEEE TC-VLSI Newsletter and ACM SIGDA e-Newsletter, and as a Guest Editor for the Proceedings of the IEEE and ACM Transactions on Cyber-Physical Systems (TCPS). He is the Conference Chair of IEEE TCCPS. Dr. Zhu has served on the technical program committee and as organizer for a number of conferences in design automation, cyber-physical systems, embedded systems, and real-time systems, including DAC, ICCAD, DATE, ASP-DAC, ICCPS, CODES+ISSS, RTSS, RTAS, ICESS, GLVLSI, SAC, SIES, MEMOCODE, SAMOS, FDL, etc. He received the ACM SIGDA Service Award in 2015.

Affiliation(s)

Northwestern University

United States

Antennas & Propagation Society Representative

Quan Xue

City University of Hong Kong

Hong Kong SAR China

10 (Asia and Pacific)

Quan Xue

10 (Asia and Pacific)

Biography

Quan Xue received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 1988, 1991, and 1993, respectively. In 1993, he joined the UESTC, as a Lecturer. He became a Professor in 1997. From October 1997 to October 1998, he was a Research Associate and then a Research Fellow with the Chinese University of Hong Kong.

In 1999, he joined the City University of Hong Kong where he is currently a Chair Professor of Microwave Engineering. He also served the University as the Associate Vice President (Innovation Advancement and China Office) (June 2011-Jan 2015), and is now the Director of Information and Communication Technology Center (ICTC center), and the Deputy Director of the State Key Lab of Millimeter Waves (Hong Kong).

He has authored or co-authored over 300 internationally referred journal papers and over 160 international conference papers. He is co-inventor of 5 granted Chinese patents and 17 granted US patents, in addition to 26 filed patents. His research interests include microwave/millimeter-wave/THz passive components, active components, antenna, microwave monolithic integrated circuits (MMIC, and radio frequency integrated circuits (RFIC), etc. Professor Xue is a Fellow of IEEE. He served the IEEE as an AdCom member of MTT-S (2011-2013) and the Associate Editor of IEEE Transactions on Microwave Theory and Techniques (2010-2013), the Editor of International Journal of Antennas and Propagation (2010-2013), the Associate Editor of IEEE Transactions on Industrial Electronics (2010-2015). He is now an Associate Editor of IEEE Transactions on Antennas and Propagation (2016-present).

Affiliation(s)

City University of Hong Kong

Hong Kong SAR China

Circuits & Systems Society Representative

Ricardo Reis

Universidade Federal do Rio Grande do Sul

Brazil

9 (Latin America)

Computer Society Representative

Dimitrios Serpanos

University Of Patras

Greece

8 (Africa, Europe, Middle East)

Electron Devices Society Representative

David Pan

University of Texas at Austin

United States

5 (Southwestern U.S.)

Electronics Packaging Society Representative

Christopher Bailey

University of Greenwich

United Kingdom

8 (Africa, Europe, Middle East)

Christopher Bailey

8 (Africa, Europe, Middle East)

Biography

CHRIS BAILEY (A’01, M’03, SM’05) is a Professor of Computational Mechanics and Reliability at the University of Greenwich, London, United Kingdom. "I received my PhD in Computational Modelling from Thames Polytechnic in 1988, and an MBA in Technology Management from the Open University in 1996. Before joining Greenwich in 1991, I worked for three years at Carnegie Mellon University (USA) as a research fellow in materials engineering.

One of my main achievements with regard to CPMT was helping to establish the Region 8 flagship conference ESTC (Electronics System-integration Technology Conference). I was the Programme Chair for the first conference held in Dresden and was the General Chair for the 2008 conference in London. In 2007 I was the local chair for the IEEE EPS sponsored EuroSime conference held in London, and since 2009 have worked with the EuroSime team as co-editor of the proceedings and track chair for multi-physics modelling.

Since 2010 I have had the pleasure of serving you as a member of the CPMT Board of Governors. During my first term on the BoG, I also took on the role of Strategic Director for Student Programs with the aim of supporting students involved in CPMT activities worldwide. Particular achievements include arranging financial support for student attendees at the International Spring Seminar on Electronics Technology (ISSE) as well as promoting student membership at events such as ECTC, EPTC, and ESTC.
Other CPMT activities that I have been involved with include membership of technical committees for EPTC (Singapore), Eurosime (Europe), ISSE (Europe) and ICEP/HDP (China) where I am a regular attendee and presenter. I have also worked closely with others in Europe to help promote closer co-operation between CPMT and IMAPS for the benefit of the whole community.

My research has resulted in over 250 publications. I am currently an Associate Editor for the CPMT Transactions and have been a guest editor on the journal of Soldering and Surface Mount Technology. I am also a committee member of the Innovative Electronics Manufacturing Research Centre (IeMRC) in the UK and have participated in a number of UK Government-sponsored overseas missions to promote collaboration and review electronic packaging technologies. Recently I became a member of the working group writing a new IEEE standard for Prognostics and Health Management for Electronic Systems."

Affiliation(s)

University of Greenwich

United Kingdom

Electronics Packaging Society Alternate

José Schutt-Ainé

University of Illinois

United States

4 (Central U.S.)

José Schutt-Ainé

4 (Central U.S.)

Biography

José E. Schutt-Ainé (S’86–M’86–SM’98–F’07) received the B.S. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, MA, USA, in 1981, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana–Champaign (UIUC), Urbana, IL, USA, in 1984 and 1988, respectively.

From 1981 to 1983, he was with the Hewlett Packard Technology Center, Santa Rosa, CA, USA, as an Application Engineer, where he was involved in research on microwave transistors and high-frequency circuits. In 1988, he joined the Electrical and Computer Engineering Department, UIUC, as a member of Electromagnetics and Coordinated Science Laboratories, where he is currently involved in research on signal integrity for high-speed digital and high-frequency applications. He is a consultant for several corporations. His current research interests include the study of signal integrity and the generation of computer-aided design tools for high-speed digital systems.

Dr. Schutt-Ainé was a recipient of several research awards, including the 1991 National Science Foundation (NSF) MRI Award, the NASA Faculty Award for Research, in 1992, the NSF MCAA Award, in 1996, and the UIUC-NCSA Faculty Fellow Award, in 2000. He has also received several publication awards, including the IEEE Electrical Design of Advanced Packaging and Systems Symposium-2013 Best Paper Award and the IEEE Electrical Performance of Electronic Packaging-2014 Best Paper Award. He is currently serving as the Co-Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology.

Affiliation(s)

University of Illinois

United States

Microwave Theory & Techniques Society Representative

José E. Rayas-Sánchez

Instituto Tecnológico y de Estudios Superiores de Occidente

Mexico

9 (Latin America)

José E. Rayas-Sánchez

9 (Latin America)

Biography

José Ernesto Rayas-Sánchez received the B.Sc. degree in electronics engineering from ITESO–The Jesuit University of Guadalajara, Tlaquepaque, Mexico, the M.Sc. degree in electrical engineering from Monterrey Tec (ITESM), Monterrey, Mexico, and the Ph.D. degree in electrical engineering from McMaster University, Ontario, ON, Canada.

He is currently a Profesor Numerario (Hons.) with ITESO–The Jesuit University of Guadalajara, where he is the Chair of the Doctoral Program in Engineering Sciences, and leads the Research Group on Computer-Aided Engineering of Circuits and Systems (CAECAS). His current research interests include computer-aided and knowledge-based modeling, design and optimization of high-frequency electronic circuits and devices (including RF, microwave, and wireless circuits).

Dr. Rayas-Sánchez is a member of the Technical Program Reviewers Committee of the IEEE MTT-S International Microwave Symposium (IMS). He is the Chair of the Technical Committee on Computer-Aided Design (MTT-1) of the IEEE Microwave Theory and Techniques Society (MTT-S). He serves as a Reviewer for the following publications: the IEEE Transactions on Microwave Theory and Techniques, IEEE Microwave and Wireless Components Letters, IEEE Antennas and Wireless Propagation Letters, the IET Microwaves, Antennas and Propagation Journal, the International Journal on Numerical Modelling (Wiley), and the International Journal of RF and Microwave Computer-Aided Engineering (Wiley). Since 2013, he has been an IEEE MTT-S Regional Coordinator for Latin America. He was the General Chair of the First IEEE MTT-S International Microwave Workshop Series in Region 9 (IMWS2009-R9) on Signal Integrity and High-Speed Interconnects (Guadalajara, Mexico, 2009), as well as the General Chair of the First IEEE MTT-S Latin America Microwave Conference (LAMC-2016, Puerto Vallarta, Mexico, 2016).

Affiliation(s)

Instituto Tecnológico y de Estudios Superiores de Occidente

Mexico

Solid-State Circuits Society Representative

Bryan Ackland

Stevens Institute of Technology

United States

2 (Eastern U.S.)

Solid-State Circuits Society Alternate

Vivek Tiwari

Intel Corp.

United States

6 (Western U.S.)

Design&Test Editor-in-Chief

Jörg Henkel

Karlsruhe Institute of Technology (KIT)

Germany

8 (Africa, Europe, Middle East)

Jörg Henkel

8 (Africa, Europe, Middle East)

Biography

Prof. Jörg Henkel is with Karlsruhe Institute of Technology (KIT), Germany, where he is directing the Chair for Embedded Systems CES. Before, he was a Senior Research Staff Member at NEC Laboratories in Princeton, NJ. He received his PhD from Braunschweig University with "Summa cum Laude".

Prof. Henkel has/is organizing various embedded systems and low power ACM/IEEE conferences/symposia as General Chair and Program Chair and was a Guest Editor on these topics in various journals like the IEEE Computer Magazine.

He was Program Chair of CODES'01, RSP'02, ISLPED’06, SIPS'08, CASES'09, Estimedia'11, VLSI Design'12, ICCAD’12, PATMOS’13, NOCS’14 and served as General Chair for CODES'02, ISLPED’09, Estimedia’12, ICCAD’13 and ESWeek'16. He is/has been a steering committee member of major conferences in the embedded systems field like at ICCAD, ESWeek, ISLPED, Codes+ISSS, CASES and is/has been an editorial board member of various journals like the IEEE TVLSI, IEEE TCAD, IEEE TMSCS, ACM TCPS, JOLPE, etc.

In recent years, Prof. Henkel has given more than ten keynotes at various international conferences primarily with focus on embedded systems dependability. He has given full/half-day tutorials at leading conferences like DAC, ICCAD, DATE, etc. Prof. Henkel received the 2008 DATE Best Paper Award, the 2009 IEEE/ACM William J. Mc Calla ICCAD Best Paper Award, the Codes+ISSS 2015, 2014, and 2011 Best Paper Awards, and the MaXentric Technologies AHS 2011 Best Paper Award as well as the DATE 2013 Best IP Award and the DAC 2014 Designer Track Best Poster Award. He is the Chairman of the IEEE Computer Society, Germany Section, and was the Editor-in-Chief of the ACM Transactions on Embedded Computing Systems (ACM TECS) for two consecutive terms.
He is an initiator and the coordinator of the German Research Foundation's (DFG) program on 'Dependable Embedded Systems' (SPP 1500). He is the site coordinator (Karlsruhe site) of the Three-University Collaborative Research Center on "Invasive Computing" (DFG TR89). He is the Editor-in-Chief of the IEEE Design&Test Magazine. He holds ten US patents and is a Fellow of the IEEE.

Affiliation(s)

Karlsruhe Institute of Technology (KIT)

Germany

ESL Editor-in-Chief

Preeti Ranjan Panda

Indian Institute of Technology, Delhi

India

10 (Asia and Pacific)

Preeti Ranjan Panda

10 (Asia and Pacific)

Biography

Preeti Ranjan Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine. He is currently a Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore, and the Advanced Technology Group at Synopsys Inc., Mountain View, and has been a visiting scholar at Stanford University.

His research interests are Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, Hardware/Software Codesign, and Low Power Design. He is the author of two books: Memory issues in Embedded Systems-on-chip: Optimizations and Exploration (Kluwer Academic Publishers) and Power-efficient System Design (Springer). He is a recipient of an IBM Faculty Award , the IESA Techno Mentor Award, and a Department of Science and Technology Young Scientist Award. Research works authored by Prof. Panda and his students have received several honours, including Best Paper nominations at CODES+ISSS, DATE, ASPDAC, and VLSI Design Conference, and Most downloaded paper of ACM TODAES journal.

Prof. Panda currently serves as the Editor-in-Chief of IEEE Embedded Systems Letters (ESL). He has served on the editorial boards of IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) , ACM Transactions on Design Automation of Electronic Systems (TODAES) , IEEE Embedded Systems Letters (ESL), IEEE Transactions on Multi-Scale Computing Systems (TMSCS) and International Journal of Parallel Programming (IJPP), General co-Chair of VLSI Design, and as Technical Program co-Chair of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) and International Conference on VLSI Design and Embedded Systems (VLSI Design). He has also served on the technical program committees and chaired sessions at several conferences in the areas of Embedded Systems and Design Automation, including DAC, ICCAD, DATE, CODES+ISSS, IPDPS, ASPDAC, and EMSOFT.

Affiliation(s)

Indian Institute of Technology, Delhi

India

TCAD Editor-in-Chief

Rajesh K. Gupta

University of California, San Diego

United States

6 (Western U.S.)

Rajesh K. Gupta

6 (Western U.S.)

Biography

Rajesh K. Gupta (F’91) received the B.Tech. degree in electrical engineering from Indian Institute of Technology Kanpur, Kanpur, India, in 1984, the M.S. degree in EECS from University of California, Berkeley, Berkeley, CA, USA, in 1986, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, USA, in 1994.

He is a Qualcomm Endowed Chair Professor with the Department of Computer Science and Engineering, University of California, San Diego, San Diego, CA, USA. He was a Circuit Designer with Intel Corporation, Santa Clara, CA, USA, as a member of three successful processor design teams and on the Computer Science Faculty, University of Illinois, Urbana-Champaign, Champaign, IL, USA and the University of California, Irvine, Irvine, CA, USA. Regardless of the title, the focus of the research has been on methods and tools to make things better, such as, more energy-efficient and reliable, or enable others (mostly, designers and architects) to do things better. To the extent a problem area requires it, there is a focus on creating usable artifacts or at least find the limits on what is achievable in practice. His past contributions include SystemC modeling and SPARK parallelizing high-level synthesis, both of which have been incorporated into industrial practice. His publications and patents cover various aspects of embedded systems design, design automation, clock design, data-path synthesis, system-on-chip modeling, and dynamic power management. He was a Lead or a Co-Lead of DARPA-sponsored efforts under the data-intensive systems and power-aware computing and communications programs on the role of adaptation in energy-efficient system architectures. His ongoing projects are focused on efficient compositional synthesis of system-chips, microelectronic variability, accurate timing, and synchronization for the integrated systems. His current research interests include embedded,cyber-physical systems, and Internet-of-Things.

Dr. Gupta was a recipient of the Best Demonstration Paper Award at ACM BuildSys’16, the Best Paper Award at IEEE/ACM DCOSS’08, and the Best Demonstration Award at IEEE/ACM IPSN/SPOTS’05 with and his students. He is a fellow of the ACM.

Affiliation(s)

University of California, San Diego

United States

Design Automation TC Chair

Iris Hui-Ru Jiang

National Taiwan University

Taiwan

10 (Asia and Pacific)

Iris Hui-Ru Jiang

10 (Asia and Pacific)

Biography

Iris Hui-Ru Jiang received the B.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan. She has been with National Chiao Tung University, Hsinchu, Taiwan, from 2005 to 2017. She is currently a Professor with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan. She has been a Visiting Scholar with IBM Austin Research Laboratory, Austin, TX, USA, from 2013 to 2014. Her current research interests include physical design optimization, interaction between logic design and physical synthesis, timing analysis and optimization, design for manufacturability, and data analytics-based design automation.

Dr. Jiang was a recipient of the Best Paper Award Nomination from Design Automation Conference (DAC) 2016 and International Symposium on Physical Design (ISPD) 2013, the Best in-track Paper Award from International Conference on Computed Aided Design (ICCAD) 2014, the 2011 Outstanding Young Electrical Engineer Award and 2018 Outstanding Electrical Engineering Professor Award from Chinese Institute of Electrical Engineering. She and her students were the recipients of the First Place Award at the CAD Contest at ICCAD in 2012, two Third Place Awards at the TAU Timing Analysis Contests in 2013 and 2014, four First Place Awards at the TAU Timing Analysis Contest in 2015, 2017, 2018, and 2019.

She is currently the Chair of IEEE CEDA Design Automation Technical Committee and has organized CAD contest at ICCAD from 2012 to 2014 and [email protected], since 2016. She is currently an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and has served on technical program committees of major EDA conferences, including DAC, ICCAD, ISPD, etc. She is a member of the Phi Tau Phi Scholastic Honor Society.

Affiliation(s)

National Taiwan University

Taiwan

System Validation & Debug TC Chair

Chinna Prudvi

Intel Corp.

United States

6 (Western U.S.)

Test Technology TC Chair

Giorgio Di Natale

CNRS/TIMA

Italy

8 (Africa, Europe, Middle East)

TC on Cyber-Physical Systems Chair

Shiyan Hu

University of Southampton

United Kingdom

8 (Africa, Europe, Middle East)

Shiyan Hu

8 (Africa, Europe, Middle East)

Biography

Professor Shiyan Hu received his Ph.D. in Computer Engineering from Texas A&M University in 2008. Currently, he is a Professor (Chair in Cyber-Physical System Security) at University of Southampton. His research interests include Cyber-Physical Systems and Cyber-Physical System Security, where he has published more than 100 refereed papers, including 50+ in premier IEEE Transactions. He is an ACM Distinguished Speaker, an IEEE Systems Council Distinguished Lecturer, a recipient of the 2017 IEEE Computer Society TCSC Middle Career Researcher Award, and a recipient of the 2014 U.S. National Science Foundation (NSF) CAREER Award. His publications have received distinctions such as the 2018 IEEE Systems Journal Best Paper Award, the 2017 Keynote Paper in IEEE Transactions on Computer-Aided Design, the Front Cover Paper in IEEE Transactions on Nanobioscience in March 2014, Thomson Reuters ESI Highly Cited Paper 2017-2019, etc. His research has been featured in various public media such as National Science Foundation News Headlines, Science Daily, CBS, IEEE Spectrum, and Communications of ACM. He is the Chair for IEEE Technical Committee on Cyber-Physical Systems. He is the Editor-In-Chief of IET Cyber-Physical Systems: Theory & Applications. He is an Associate Editor for IEEE Transactions on Computer-Aided Design, IEEE Transactions on Industrial Informatics, IEEE Transactions on Circuits and Systems, ACM Transactions on Design Automation for Electronic Systems, and ACM Transactions on Cyber-Physical Systems. He is also a Guest Editor for eight IEEE/ACM journals such as Proceedings of the IEEE and IEEE Transactions on Computers. He has held chair positions in many conferences.

Affiliation(s)

University of Southampton

United Kingdom

ASP-DAC Representative

Kazutoshi Wakabayashi

NEC Corporation

Japan

10 (Asia and Pacific)

DAC Representative

Ayse Coskun

Boston University

United States

1 (Northeastern U.S.)

DATE Representative

Donatella Sciuto

Politecnico di Milano

Italy

8 (Africa, Europe, Middle East)

ICCAD Representative

Tsung-Yi Ho

National Tsing Hua University

Taiwan

10 (Asia and Pacific)

Tsung-Yi Ho

10 (Asia and Pacific)

Biography

Affiliation(s)

National Tsing Hua University

Taiwan

Fellow Evaluation Committee Chair

Xiaobo Sharon Hu

University of Notre Dame

United States

4 (Central U.S.)

Diversity & Inclusion Chair*

Chengmo Yang

University of Delaware

United States

2 (Eastern U.S.)

IEEE WIE Representative*

Agnieszka Dubaj

Intel Corp.

United States

6 (Western U.S.)

IEEE Division I Director (ex-officio)

Alfred E. Dunlop

IEEE Vice President, Technical Activities (ex-officio)

Kazuhiro Kosuge

Tohoku University

Japan

10 (Asia and Pacific)

Social Media Coordinator*

Sudeep Pasricha

Colorado State University

United States

5 (Southwestern U.S.)

Sudeep Pasricha

5 (Southwestern U.S.)

Biography

Sudeep Pasricha is a Monfort Professor and Rockwell-Anderson Professor in the Department of Electrical and Computer Engineering and the Department of Computer Science at Colorado State University, where he is also the Chair of Computer Engineering and Director of the Embedded Systems and High-Performance Computing (EPiC) Laboratory. His research interests are broadly in the areas of energy-efficient, fault-resilient, and secure computing, for platforms encompassing embedded systems (cyber-physical systems), mobile computing (internet-of-things), and high-performance computing (datacenters, supercomputers). More specific topics of interest include: 1) on-chip and chip-to-chip network design, 2) memory architecture design, 3) design with emerging technologies, e.g., silicon photonics, 4) middleware and embedded software design, 5) algorithms for multi-objective optimization, 6) real-time system design, and 7) VLSI design, and 8) resource allocation/scheduling techniques. He also works on applications of technology to automotive systems (he is the ECE faculty lead for the controls and ADAS design activities on the Ecocar3 project, and also involved with powertrain control software development for a leading automotive company), robotics, therapy, mobile sensing, smart infrastructure, and workflow automation. Details of ongoing and past research projects can be found here.

Prof. Pasricha received the B.E. degree in electronics and communication engineering from Delhi Institute of Technology, Delhi, India, in 2000, and his M.S. and Ph.D. degrees in computer science from the University of California, Irvine in 2005 and 2008. He joined Colorado State University (CSU) in 2008. Prior to joining CSU, he spent several years working in semiconductor companies including STMicroelectronics and Conexant. He has written a book, contributed several book chapters, and published over 160 research articles in peer-reviewed conferences and journals that have received more than 2600 citations. He holds a patent and has presented several tutorials at premier conferences. He has graduated 6 Ph.D. and 8 M.S students.

His research has been recognized with five Best Paper Awards at the ACM SLIP 2016, ACM GLSVLSI 2015, IEEE AICCSA 2011, IEEE ISQED 2010 and ACM/IEEE ASPDAC 2006 conferences, as well as three Best Paper Award Finalist selections at IEEE ISQED 2016, IEEE SCNS 2016, and ACM/IEEE DAC 2005. He has received several fellowships and awards for excellence in research and teaching, including the 2016-2019 Walter Scott Jr. College of Engineering Rockwell-Anderson Professorship, the 2016-2018 University Distinguished Monfort Professorship, the 2015 IEEE/TCSC Award for Excellence for a mid-career researcher, and the 2014 George T. Abell Outstanding mid-career faculty award. His research is sponsored by research grants from the National Science Foundation (NSF), Semiconductor Research Corporation (SRC), Fiat-Chrysler Corporation, Air Force Office of Scientific Research (AFOSR), Oak Ridge National Lab (ORNL), and National Aeronautics and Space Administration (NASA), including the AFOSR Young Investigator Award in 2013, as well as grants from Intel, HP, AMD, Microsoft, Xilinx, Altera, ARM, and RIM/Blackberry.

Affiliation(s)

Colorado State University

United States

Council Operations Manager*

Brooke Johnson

Council Operations Manager

Conference Catalysts, LLC

United States