Cheng Zhuo

As Moore's law is approaching to the end, designing specialized hardware along with the software that maps the applications onto that hardware is a promising solution. The peak performance of the hardware design is important, while the software also plays a critical role in determining the actual performance. The recent progress in computing-in-memory (CiM) using non-volatile memory (NVM) demonstrates its potential as a specialized accelerator to enhance energy efficiency, particularly at the edge. It is expected that the hardware/software (HW/SW) co-design can further optimize NVM based CiMs and improve the overall performance. However, the current process for HW/SW co-design in CiM has not been well addressed. Additionally, it is difficult to design and optimize NVM based CiMs due to the huge design space. Thus, in this talk, we will introduce novel co-exploration frameworks for algorithms, CiM architectures and various device options including FeFET, ReRAM, and MRAM. We will showcase how our flexible co-exploration framework, Eva-CiM, broadens the design freedom and advances the Pareto frontier between hardware efficiency and algorithm performance for better design trade-offs. Furthermore, we will present the unified optimization of HW/SW to minimize the impact of intrinsic reliability issues in CiM.

Approximate computing is an effective approach to enhance circuit performance and energy efficiency by deliberately sacrificing accuracy. Among various arithmetic units, multiplication is a widely used but possibly the most energy-consuming operation. Its approximate variants have received growing interests from both academia and industry. However, the accuracy and energy efficiency of these approximations can vary greatly depending on how and where they are introduced into the design. This talk will first review various approximation techniques for multiplier design, ranging from circuit- to algorithm-level approaches. Then, we will delve into the recent developments in cross-layer approximate multiplier design, which combines circuit-level customization and algorithm-level optimization. Such a cross-layer perspective can address the above concerns by linking the algorithm specification to the circuit details to achieve the desired energy efficiency. We will also present results from RTL implementations in comparison to the prior works, demonstrating that the cross-layer methodology can lead to almost an order of magnitude improvement in energy efficiency with minimal accuracy loss.

Relentless scaling in semiconductors and the growing complexity of System-on-Chip (SoC) integration have presented various challenges in design sign-off, from problem size to formulation complexity. On the other hand, the success of Machine Learning (ML), particularly deep learning, has sparked widespread interest in ML-powered design automation. A notable example is Google's Placer, which uses deep reinforcement learning and has garnered much attention in academia and industry. It's important to note that unlike many computer vision problems, sign-off problems already have a well-established mathematical and physical law-based system. This raises questions about the scope and effectiveness of ML techniques in sign-off Electronic Design Automation (EDA). Moreover, sign-off verification requires high accuracy and, in some cases, exact solutions, while ML techniques are known to result in unpredictable accuracy loss. This talk will start with a comprehensive overview of the directions in which ML will improve the cost and efficiency of sign-off. It will then delve into the successful applications of ML in power and timing sign-off, as well as its deployment in industrial practices to speed up sign-off convergence. Finally, the talk will summarize the lessons we learned during this trip of bringing ML to sign-off problems.