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Data-Driven Deep Learning for Full-Chip Thermal and Power Estimation for Commercial Multi-core Systems


Sheldon Tan

University of California, Riverside

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Recently machine learning, especially deep learning is gaining much attention due to the breakthrough performance in various cognitive tasks. Machine learning for electronic design automation is also gaining traction as it provides new techniques for many of the challenging design automation problems with complex nature.

In this talk, I will present our recent work from VSCLAB at UC Riverside on machine learning-based thermal map and power density map estimation methods for commercial multi-core CPUs. First I will look at the real-time full-chip thermal map estimation problem for commercial multi-chip processors. In our work, instead of using traditional functional unit powers as input, the new models are directly based on the on-chip real-time high-level chip utilization and thermal sensor information of commercial chips without any assumption of additional physical sensors requirement. We first framed the problem as the static or transient mapping between the chip utilizations and thermal maps. To build the transient thermal model, we utilized temporal-aware long-short-term-memory (LSTM) neural networks with system-level variables such as chip frequency, voltage, and instruction counts as inputs. Instead of a pixel-wise heatmap estimation, we used 2D spatial discrete cosine transformation (DCT) on the heatmaps so that they can be expressed with just a few dominant DCT coefficients. Second, we explored generative learning for the full-chip thermal map estimation problem. In our work, we treated the thermal modeling problem as an image-generation problem using the generative neural networks. The resulting thermal map estimation method, called ThermGAN can provide tool-accurate full-chip transient thermal maps from the given performance monitor traces of commercial off-the-shelf multi-core processors. Third, I will present a new full-chip power map estimation method for commercial multi-core processors.