Special Section On Circuit And System Design Automation For Internet Of Things

Editorial

Guest Editorial

Special Section Papers

Microprocessor Optimizations for the Internet of Things: A Survey

The Internet of Things (IoT) refers to a pervasive presence of interconnected and uniquely identifiable physical devices. These devices' goal is to gather data and drive actions in order to improve productivity, and ultimately reduce or eliminate reliance on human intervention for data acquisition, interpretation, and use. The prolifer...

Read more...

Multicore Mixed-Criticality Systems: Partitioned Scheduling and Utilization Bound

The Internet of Things (IoT) refers to a pervasive presence of interconnected and uniquely identifiable physical devices. These devices' goal is to gather data and drive actions in order to improve productivity, and ultimately reduce or eliminate reliance on human intervention for data acquisition, interpretation, and use. The prolifer...

Read more...

Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA

Convolutional neural network (CNN) has become a successful algorithm in the region of artificial intelligence and a strong candidate for many computer vision algorithms. But the computation complexity of CNN is much higher than traditional algorithms. With the help of GPU acceleration, CNN-based applications are widely deployed in serv...

Read more...

YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration

Convolutional neural networks (CNNs) have revolutionized the world of computer vision over the last few years, pushing image classification beyond human accuracy. The computational effort of today's CNNs requires power-hungry parallel processors or GP-GPUs. Recent developments in CNN accelerators for system-on-chip integration have red...

Read more...

High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds

Asynchronous circuits are becoming increasingly important in system design for Internet of Things, where they orchestrate the interface between big synchronous computation components and the analog environment, which is inherently asynchronous and has high uncertainty with respect to power supply, temperature, and long-term aging effec...

Read more...

qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses

Multisocket computer systems are popular in workstations and servers. However, they suffer from the relatively low bandwidth of intersocket communication especially for massive parallel workloads that generate many intersocket requests for synchronizations and remote memory accesses. Intersocket traffic puts pressure on the underlying ...

Read more...

Enabling Security-Enhanced Attestation With Intel SGX for Remote Terminal and IoT

Along with the advent and popularity of cloud computing, Internet of Things, and bring your own device, the trust requirement for terminal devices has increased significantly. An untrusted terminal, a terminal that runs in an untrustworthy execution environment, may cause serious security issues for enterprise networks. With the releas...

Read more...

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF

Today, life is becoming increasingly connected. From TVs to smartphones, including vehicles, buildings, and household appliances, everything is interconnected in what we call the °ßInternet of Things°® (IoT). IoT is now part of our life and we have to deal with it. More than ten billion devices are already connected and five times more...

Read more...

On Random Dynamic Voltage Scaling for Internet-of-Things: A Game-Theoretic Approach

Security is one of the top considerations in hardware designs for Internet-of-Things (IoT), where embedded cryptosystems are extensively used. Traditionally, random dynamic voltage scaling technology has been shown to be very effective in improving the resistance of cryptosystems against side-channel attacks. However, in this paper we ...

Read more...

Toward Smart Building Design Automation: Extensible CAD Framework for Indoor Localization Systems Deployment

Over the last years, many smart buildings applications, such as indoor localization or safety systems, have been subject of intense research. Smart environments usually rely on several hardware nodes equipped with sensors, actuators, and communication functionalities. The high level of heterogeneity and the lack of standardization acro...

Read more...

A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications

In this paper, a fully synthesizable all-digital transmitter (ADTX) is first proposed. This transmitter (TX) uses Cartesian architecture and supports wide-band quadratic-amplitude modulation with wide carrier frequency range. Furthermore, the design methodology for ADTX and corresponding bandpass filter is discussed. This TX is synthes...

Read more...

Regular Papers

Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives

Solid state drives (SSDs) have been widely deployed in personal computers, data centers, and cloud storages. In order to improve performance, SSDs are usually constructed with a number of channels with each channel connecting to a number of nand flash chips, each flash chip consisting of multiple dies and each die containing multiple p...

Read more...

Design of Application-Specific Architectures for Networked Labs-on-Chips

Labs-on-Chips (LoCs) implement laboratory procedures on a single chip and are successfully used for chemical and biomedical applications. A promising and emerging realization of such chips are Networked LoCs (NLoCs) in which small volumes of fluids, so-called droplets, flow in closed channels of submillimeter diameters. NLoCs allow for...

Read more...

Exact Timing Analysis for Asynchronous Systems

Analyzing the timing properties of asynchronous systems is essential for characterizing their performance and power. Previous work on timing showed that such systems under and-causality and fixed delay exhibit periodicity properties. We give a different graph-based rigorous proof of the exact timing behavior of more general classes of ...

Read more...

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques

Detailed routing is an important stage in very large scale integrated physical design. Due to the extreme scaling of transistor feature size and the complicated design rules, ensuring routing completion without design rule checking (DRC) violations becomes more and more difficult. Studies have shown that the low routing quality partly ...

Read more...

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations

As very large scale integration technology scales to deep submicrometer and beyond, interconnect delay greatly limits the circuit performance. The traditional 2-D global routing and subsequent net by net assignment of available empty tracks on various layers lacks a global view for timing optimization. To overcome the limitation, this ...

Read more...

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint

Clock network should be optimized to reduce clock power dissipation. The power efficient clock network can be constructed by multibit flip-flop generation and gated clock tree aware flip-flop clumping to pull flip-flops close to the same integrated clock gating cell. It is capable of providing an attractive solution to reduce clock pow...

Read more...