TCAD Editorial Board | IEEE Council on Electronic Design Automation

TCAD Editor-in-Chief

David Atienza

Ecole Polytechnique Fédérale de Lausanne (EPFL)

Switzerland

8 (Africa, Europe, Middle East)

David Atienza

8 (Africa, Europe, Middle East)

Biography

David Atienza Alonso received his MSc and PhD degrees in Computer Science and Engineering from Complutense Univ. of Madrid (UCM), Spain, and IMEC, Belgium, in 2001 and 2005. Currently, he is an associate professor of electrical and computer engineering, and head of the Embedded Systems Laboratory (ESL) at the Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland. His research interests include system-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) and low-power Internet-of-Things (IoT) systems, including new 2-D/3-D thermal-aware design for MPSoCs and many-core servers, ultra-low power system architectures for wireless body sensor nodes and edge computing, HW/SW reconfigurable systems, dynamic memory optimizations, and network-on-chip design. He is a co-author of more than 250 publications in peer-reviewed international journals and conferences, several book chapters, and eight U.S. patents in these fields. He has earned several best paper awards and he is (or has been) an Associate Editor of IEEE TC, IEEE D&T, IEEE T-TCAD, IEEE T-SUSC and Elsevier Integration. He was the Technical Programme Chair of IEEE/ACM DATE 2015 and General Programme Chair of IEEE/ACM DATE 2017. Dr. Atienza received the DAC Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He is an IEEE Fellow and an ACM Distinguished Member.

Affiliation(s)

Ecole Polytechnique Fédérale de Lausanne (EPFL)

Switzerland

TCAD Deputy EiC

Ayse Coskun

Boston University

United States

1 (Northeastern U.S.)

TCAD Managing Editor

Sara Dailey

Dailey EAS, LLC

United States

4 (Central U.S.)

TCAD Webmaster

Ing-Chao Lin

National Cheng Kung University

Taiwan

10 (Asia and Pacific)

TCAD Associate Editors

3D Design & Optimization

Puneet Gupta

University of California, Los Angeles

United States

6 (Western U.S.)

Cheng Zhuo

Zhejiang University

China

10 (Asia and Pacific)

Cheng Zhuo

10 (Asia and Pacific)

Biography

Dr. Cheng Zhuo received B.S. degree from ChuKeChen College with major in Electrical Engineering and M.S. degree from Physical Electronics, in 2005 and 2007 respectively, in Zhejiang University. He received Ph.D degree in Computer Science & Engineering in 2010 from University of Michigan, Ann Abror. After graduation he joined Intel Corp., USA, in 2011 and led multiple research projects at Intel. In 2016, he joined Zhejiang University as a Professor and PhD Advisor. His current research interests include 3D integration, power and signal integrity, cyber physical system for medical applications, hardware accelorator and general VLSI EDA areas.

Dr. Zhuo has been invited to serve as an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE VLSI Circuits and Systems Letter, and Elsevier Integration, the VLSI Journal. He was a Guest editor for IET Cyber Physical System. He has also served in many technical program committees of top conferences in VLSI and EDA areas. He organized/co-organized ACM/SIGDA student research contest in 2017/2018, ISPD gate sizing contests in 2012/2013, SLIP 2105-2017, CSTIC 2018-2019, and special sessions in top conferences. He has been frequently invited as reviewers for international journals and conferences for VLSI design. He has published more than 60 peer-reviewed papers and coauthored 1 book chapter. He has received 4 Intel Division Recognition awards, 2012 ACM SIGDA technical leadership award, 2016 DAC Best Paper Nomination, 2017 JSPS Invitation Fellowship, 2018 CSTIC Best Student Paper Nomination, and 2018 DAC System Design Contest 2nd Place. He is a senior member of IEEE.

Affiliation(s)

Zhejiang University

China

Analog & Mixed Signal

Peng Li

University of California, Santa Barbara

United States

6 (Western U.S.)

Peng Li

6 (Western U.S.)

Biography

I received the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA in 2003 and the M. Eng. degree in systems engineering and B.Eng. degree in information science & engineering from Xi’an Jiaotong University, Xi’an, China, in 1997 and 1994, respectively.

I have been a Professor of ECE at UCSB since July 2019, where I'm affiliated with the Computer Engineering (CE) Program. From August 2004 to June 2019, I was with the Department of Electrical and Computer Engineering at Texas A&M University as an assistant, associate, and then a full professor. I was was a member of Faculty of Neuroscience and the Graduate Faculty of School of Graduate Studies, Health Science Center at Texas A&M.

My research interests are in integrated circuits and systems, learning algorithms and circuits for neuromorphic (a.k.a brain-inspired) computing, VLSI computer-aided design, machine learning and its hardware realization in VLSI, and computational brain modeling. I am a co-editor of the book, entitled "Simulation and Verification of Electronic and Biological Systems" (Springer, 2011), co-edited one additional book, and authored and co-authored over 200 journal and conference publications, and seven book chapters.

My work has been recognized by various distinctions including the ICCAD Ten Year Retrospective Most Influential Paper Award in 2019, four IEEE/ACM Design Automation Conference (DAC) Best Paper Awards in 2003, 2008, 2011, and 2016, the ISCAS Honorary Mention Best Paper Award from the Neural Systems and Applications Technical Committee of IEEE Circuits and Systems (CAS) Society at IEEE International Symposium on Circuits and Systems (ISCAS) in 2016, the IEEE/ACM William J. McCalla ICCAD Best Paper Award from IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2012, the US National Science Foundation CAREER Award in 2008, two Inventor Recognition Awards from Microelectronics Advanced Research Corporation (MARCO) in 2006 and 2007, two Semiconductor Research Corporation (SRC) Inventor Recognition Awards in 2001 and 2004. At the 50th IEEE/ACM Design Automation Conference in 2013, I was honored with the Best Paper Hat Trick Award for receiving the prestigious DAC best paper award three times, the DAC Prolific Author Award, and the DAC Top 10 Author in Fifth Decade Award. I recieved several Best Paper Award nominations from ICCAD. At Texas A&M, I was recongnized with the 2018-2019 Eugene E. Webb Faculty Fellow, 2013-2014 William and Montine P. Head Fellow, 2011-2012 TEES Fellow Award from the College of Engineering, and the ECE Outstanding Professor Award in 2008.

I was an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems from 2008 to 2013 and an associate editor for IEEE Transactions on Circuits and Systems II from 2008 to 2016. I have been on the committees of many international conferences and workshops such as DAC, ISLPED, IJCNN, ICCAD, ICCD, ISQED, ISCAS, TAU and FAC, ICCAD Best Paper Award Committee, and the selection committee for ACM Outstanding Ph.D. Dissertation Award in Electronic Design Automation. He served as the technical program committee chair for the ACM TAU Workshop in 2009 and general chair for the 2010 Workshop. I was a member of the Executive Committee and the Vice President for Technical Activities of IEEE Council on Electronic Design Automation (CEDA) from Jan. 2016 to Dec. 2017.

I have consulted for Intel Corporation and several Silicon-Valley startup companies. I am a Fellow of the IEEE and a member of the ACM.

Affiliation(s)

University of California, Santa Barbara

United States

Linda Milor

Georgia Tech

United States

5 (Southwestern U.S.)

Georges Gielen

KU Leuven

Belgium

8 (Africa, Europe, Middle East)

Approximate Computing

Xun Jiao

Villanova University

United States

2 (Eastern U.S.)

Gang Qu

University of Maryland

United States

2 (Eastern U.S.)

Architectural Design & Optimization

Katzalin Olcoz

Universidad Complutense de Madrid

Spain

8 (Africa, Europe, Middle East)

Francesco Conti

Università di Bologna

Italy

8 (Africa, Europe, Middle East)

Automation for Emerging Technologies

Philip Brisk

University of California, Riverside

United States

6 (Western U.S.)

Suman Chakraborty

Indian Institute of Technology, Kharagpur

India

10 (Asia and Pacific)

Tsung-Yi Ho

National Tsing Hua University

Taiwan

10 (Asia and Pacific)

Tsung-Yi Ho

10 (Asia and Pacific)

Biography

Tsung-Yi Ho (SM’10) received the Ph.D. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2005. He is a Professor with the Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. He has presented ten tutorials and contributed 11 special sessions in ACM/IEEE conferences, all in design automation for microfluidic biochips. His research interests include design automation and test for microfluidic biochips and nanometer integrated circuits.

Dr. Ho is the recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science, the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, and the Hans Fischer Fellowship by the Institute of Advanced Study, Technical University of Munich. He was a recipient of the Best Paper Awards at the VLSI Test Symposium in 2013 and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2015. He served as a Distinguished Visitor of the IEEE Computer Society for 2013–2015, the Chair of the IEEE Computer Society Tainan Chapter for 2013–2015, and the Chair of the ACM SIGDA Taiwan Chapter for 2014–2015. He is currently an ACM Distinguished Speaker, a Distinguished Lecturer of the IEEE Circuits and Systems Society, and an Associate Editor for the ACM Journal on Emerging Technologies in Computing Systems, the ACM Transactions on Design Automation of Electronic Systems, the ACM Transactions on Embedded Computing Systems, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and the Technical Program Committees of major conferences, including the Design Automation Conference, the International Conference on Computer-Aided Design, the IEEE/ACM Design Automation and Test in Europe Conference, the Asia and South Pacific Design Automation Conference, the ACM/SIGDA International Symposium on Physical Design, and the International Conference on Computer Design.

Affiliation(s)

National Tsing Hua University

Taiwan

Mathias Soeken

Microsoft

Switzerland

8 (Africa, Europe, Middle East)

Robert Wille

Technical University of Munich

Germany

8 (Africa, Europe, Middle East)

Robert Wille

8 (Africa, Europe, Middle East)

Biography

Robert Wille is a Full and Distinguished Professor at the Technical University of Munich, Germany, and Chief Scientific Officer at the Software Competence Center Hagenberg GmbH, Austria.

From 2002 to 2006, Robert Wille studied Computer Science (Diploma) at the University of Bremen. After successfully completing his doctorate in 2009 (summa cum laude), he worked as a postdoc at the University of Bremen and, since 2013, as a Senior Researcher in the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). Besides that, he served as a lecturer at the University of Applied Science Bremen from 2010 to 2012 and was a guest professor at the University of Potsdam in 2012 as well as the Technical University of Dresden in 2013/2014. From 2015 to 2022, he was Full Professor at the Johannes Kepler University Linz and head of the Institute for Integrated Circuits (at the age of 32 and as one of the youngest full professors in the field). In 2019, he founded the LIT Secure and Correct Systems Lab at JKU, and, in 2020, he additionally became Chief Scientific Officer at the Software Competence Center Hagenberg GmbH. Since 2022, he works in Munich---appointed through a "Leuchtturm"-procedure (i.e., direct appointment) and, additionally, through the "Distinguished Professorship"-program.

Robert Wille's expertise covers a broad spectrum of topics with a particular focus on the development of automatic methods for the design, simulation, verification, and test of complex systems in hard- and software. He considers conventional technologies (from formal specifications to the realization) as well as future technologies (including quantum computing, microfluidic biochips, field-coupled nanotechnologies, optical circuits, memristors, reversible circuits, and adiabatic circuits). Besides that, he frequently applies his expertise to complementary fields in cooperation with groups from other areas of Computer Science (e.g., Machine Learning, Software Development, Theoretical Computer Science, Database Systems, Operation Systems, and more) as well as Mechatronics and Electrical Engineering. Furthermore, his work on future technologies frequently exposes him to topics from physics, biology, chemistry, and optics. Also, projects with legal sciences are within his portfolio.

Since 2007, Robert Wille published more than 400 journal and conference papers in this area and was repeatedly awarded (e.g., with Best Paper Awards, e.g., at TCAD and ICCAD, an ERC Consolidator Grant, a Distinguished and a Lighthouse Professor appointment, a Google Research Award, and more). Besides that, he served as Associate Editor and Guest Editor for various renowned journals such as the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), the ACM Journal on Emerging Technologies in Computing Systems (JETC), or Springer’s Lecture Notes in Computer Science (LNCS). Additionally, he was General Chair and PC Chair for several conferences is Executive Committee Member for DATE and ICCAD, served in numerous Program Committees, and organized several tutorials, seminars, workshops, and special sessions.

For more details, please see https://www.cda.cit.tum.de/team/wille/.

Affiliation(s)

Technical University of Munich

Germany

Cyber-Physical Systems/Internet of Things

Qi Zhu

Northwestern University

United States

4 (Central U.S.)

Qi Zhu

4 (Central U.S.)

Biography

Dr. Qi Zhu is a tenured Associate Professor in the Department of Electrical and Computer Engineering (ECE) at Northwestern University. He was an Assistant Professor and later Associate Professor in the ECE Department at University of California, Riverside from 2011 to 2017, and a Research Scientist at the Strategic CAD Labs in Intel from 2008 to 2011. Dr. Zhu received a Ph.D. in EECS from University of California, Berkeley in 2008, and a B.E. in CS from Tsinghua University in 2003. His research interests include model-based design, synthesis and verification of cyber-physical systems (CPS) and Internet of Things, CPS security, embedded and real-time systems, connected and autonomous vehicles, energy-efficient buildings and infrastructures, and system-on-chip design. He received best paper awards at Design Automation Conference (DAC) 2006, DAC 2007, International Conference on Cyber-Physical Systems (ICCPS) 2013, and ACM Transactions on Design Automation of Electronic Systems (TODAES) 2016. He received the NSF CAREER award in 2016, and the IEEE TCCPS (Technical Committee on Cyber-Physical Systems) Early-Career Award in 2017. Dr. Zhu is an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IET Cyber-Physical Systems: Theory & Applications, and IEEE TCCPS Newsletter. He served as an Associate Editor for IEEE TC-VLSI Newsletter and ACM SIGDA e-Newsletter, and as a Guest Editor for the Proceedings of the IEEE and ACM Transactions on Cyber-Physical Systems (TCPS). He is the Conference Chair of IEEE TCCPS. Dr. Zhu has served on the technical program committee and as organizer for a number of conferences in design automation, cyber-physical systems, embedded systems, and real-time systems, including DAC, ICCAD, DATE, ASP-DAC, ICCPS, CODES+ISSS, RTSS, RTAS, ICESS, GLVLSI, SAC, SIES, MEMOCODE, SAMOS, FDL, etc. He received the ACM SIGDA Service Award in 2015.

Affiliation(s)

Northwestern University

United States

Marilyn Wolf

University of Nebraska Lincoln

United States

5 (Southwestern U.S.)

Paul Bogdan

University of Southern California

United States

6 (Western U.S.)

Wenchao Li

Boston University

United States

1 (Northeastern U.S.)

Aviral Shrivastava

Arizona State University

United States

6 (Western U.S.)

Aviral Shrivastava

6 (Western U.S.)

Biography

Aviral Shrivastava is an associate professor in the School of Computing, Informatics, and Decision Systems Engineering at the Arizona State University, where he has established and heads the Compiler and Microarchitecture Labs (CML).

He received his master's degree and doctorate in information and computer science from University of California, Irvine, and bachelor's degree in computer science and engineering from Indian Institute of Technology, Delhi. He is a 2011 National Science Foundation (NSF) CAREER Award recipient, and recipient of 2012 Outstanding Junior Researcher in CSE at ASU. He was also a visiting faculty member in the EECS Department at University of California, Berkeley for 2012-2014.

His research lies at the intersection of compilers and architectures of embedded and multi-core systems, with the goal of improving power, performance, temperature, energy, reliability and robustness. His research is funded by NSF and several industries including Microsoft, Raytheon Missile Systems, Intel Nvidia, and others. He serves on organizing and program committees of several premier embedded system conferences, including ISLPED, CODES ISSS, CASES and LCTES, and regularly serves on NSF and Department of Energy (DOE) review panels.

Education

Ph.D. Computer Science and Engineering, University of California-Irvine 2006
M.S. Computer Science and Engineering, University of California-Irvine 2002
Bachelor’s degree. Computer Science and Engineering, Indian Institute of Technology, Delhi 1999

Affiliation(s)

Arizona State University

United States

Embedded Security

Rajat Subhra Chakraborty

Indian Institute of Technology, Kharagpur

India

10 (Asia and Pacific)

Swaroop Ghosh

Pennsylvania State University

United States

2 (Eastern U.S.)

Swaroop Ghosh

2 (Eastern U.S.)

Biography

Swaroop Ghosh received the B.E. (Hons.) from IIT, Roorkee, India, the M.S. degree from the University of Cincinnati, Cincinnati, and the Ph.D. degree from Purdue University, West Lafayette. He is an Assistant Professor at Penn State University. Earlier, he was with the faculty of University of South Florida. Prior to that, he was a Senior Research and Development Engineer in Advanced Design, Intel Corp. At Intel, his research was focused on low power and robust embedded memory design in scaled technologies. His research interests include low-power circuits, hardware security, quantum computing and digital testing for nanometer technologies.

Dr. Ghosh served as Associate Editor of the IEEE Transactions On Computer-Aided Design (2019-) and IEEE Transactions On Circuits and Systems I (2014-2015) and as Senior Editorial Board member of IEEE Journal of Emerging Topics on Circuits and Systems (JETCAS) (2016-2018). He served as Guest Editor of the IEEE JETCAS (2015-2016) and IEEE Transactions On VLSI Systems (2018-2019). He has also served in the technical program committees of ACM/IEEE conferences such as, DAC, ICCAD, CICC, DATE, ISLPED, GLSVLSI, Nanoarch and ISQED. He served as Program Chair of ISQED (2019) and DAC Ph.D. Forum (2016) and track (co)-Chair of CICC (2017-2019), ISLPED (2017-2018) and ISQED (2016-2017).

Dr. Ghosh is a recipient of Intel Technology and Manufacturing Group Excellence Award in 2009, Intel Divisional Award in 2011, Intel Departmental Awards in 2011 and 2012, USF Outstanding Research Achievement Award in 2015, College of Engineering Outstanding Research Achievement Award in 2015, DARPA Young Faculty Award (YFA) in 2015, ACM SIGDA Outstanding New Faculty Award in 2016, YFA Director’s Fellowship in 2017, Monkowsky Career Development Award in 2018, Lutron Spira Teaching Excellence Award in 2018 and Dean's Certificate of Excellence in 2019. He is a Senior Member of the IEEE and the National Academy of Inventors (NAI), and, Associate member of Sigma Xi.

Affiliation(s)

Pennsylvania State University

United States

Yier Jin

University of Florida

United States

3 (Southeastern U.S.)

Yier Jin

3 (Southeastern U.S.)

Biography

Yier Jin is the Endowed IoT Term Professor in the Warren B. Nelms Institute for the Connected World and also an Associate Professor in the Department of Electrical and Computer Engineering (ECE) in the University of Florida (UF). Prior to joining UF, he was an assistant professor in the ECE Department at the University of Central Florida (UCF). He received his PhD degree in Electrical Engineering in 2012 from Yale University after he got the B.S. and M.S. degrees in Electrical Engineering from Zhejiang University, China, in 2005 and 2007, respectively. His research focuses on the areas of embedded systems design and security, trusted hardware intellectual property (IP) cores and hardware-software co-design for modern computing systems. He is currently focusing on the design and security analysis on Internet of Things (IoT) and wearable devices with particular emphasis on information integrity and privacy protection in the IoT era. Dr. Jin received Young Investigator Grant from Southeastern Center for Electrical Engineering Education (SCEEE) in 2015, early CAREER award from Department of Energy (DoE) in 2016, Outstanding New Faculty Award (ONFA) from ACM’s Special Interest Group on Design Automation (SIGDA) in 2017, and Young Investigator Award (YIP) from Office of Naval Research (ONR) in 2019. He also received the Best Paper Award of the 52nd Design Automation Conference in 2015, the 21st Asia and South Pacific Design Automation Conference (DAC) in 2016, the 10thIEEE Symposium on Hardware-Oriented Security and Trust (HOST) in 2017, the 2018 ACM Transactions on Design Automation of Electronic Systems (TODAES), the 28thedition of the ACM Great Lakes Symposium on VLSI (GLSVLSI) in 2018, and the Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2019. He is the IEEE Council on Electronic Design Automation (CEDA) Distinguished Lecturer.

Affiliation(s)

University of Florida

United States

Jeyavijayan Rajendran

Texas A&M University

United States

5 (Southwestern U.S.)

Nele Mentens

Leiden University / KUL

Netherlands

8 (Africa, Europe, Middle East)

Embedded Software

Preeti Ranjan Panda

Indian Institute of Technology, Delhi

India

10 (Asia and Pacific)

Preeti Ranjan Panda

10 (Asia and Pacific)

Biography

Preeti Ranjan Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine. He is currently a Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore, and the Advanced Technology Group at Synopsys Inc., Mountain View, and has been a visiting scholar at Stanford University.

His research interests are Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, Hardware/Software Codesign, and Low Power Design. He is the author of two books: Memory issues in Embedded Systems-on-chip: Optimizations and Exploration (Kluwer Academic Publishers) and Power-efficient System Design (Springer). He is a recipient of an IBM Faculty Award , the IESA Techno Mentor Award, and a Department of Science and Technology Young Scientist Award. Research works authored by Prof. Panda and his students have received several honours, including Best Paper nominations at CODES+ISSS, DATE, ASPDAC, and VLSI Design Conference, and Most downloaded paper of ACM TODAES journal.

Prof. Panda currently serves as the Editor-in-Chief of IEEE Embedded Systems Letters (ESL). He has served on the editorial boards of IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) , ACM Transactions on Design Automation of Electronic Systems (TODAES) , IEEE Embedded Systems Letters (ESL), IEEE Transactions on Multi-Scale Computing Systems (TMSCS) and International Journal of Parallel Programming (IJPP), General co-Chair of VLSI Design, and as Technical Program co-Chair of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) and International Conference on VLSI Design and Embedded Systems (VLSI Design). He has also served on the technical program committees and chaired sessions at several conferences in the areas of Embedded Systems and Design Automation, including DAC, ICCAD, DATE, CODES+ISSS, IPDPS, ASPDAC, and EMSOFT.

Affiliation(s)

Indian Institute of Technology, Delhi

India

Embedded Systems

Madhu Mutyam

Indian Institute of Technology, Madras

India

10 (Asia and Pacific)

Chengmo Yang

University of Delaware

United States

2 (Eastern U.S.)

Tulika Mitra

National University of Singapore

Singapore

10 (Asia and Pacific)

Amir Aminifar

Lund University

Sweden

8 (Africa, Europe, Middle East)

Emerging Technologies

Abdoulaye Gamatié

CNRS / LIRMM

France

8 (Africa, Europe, Middle East)

Ian O'Connor

École Centrale de Lyon

France

8 (Africa, Europe, Middle East)

FPGA

Wei Zhang

Hong Kong University of Science & Technology

Hong Kong SAR China

10 (Asia and Pacific)

Laura Pozzi

University of Lugano

Switzerland

8 (Africa, Europe, Middle East)

High-level Synthesis

Philippe Coussy

Université de Bretagne-Sud

France

8 (Africa, Europe, Middle East)

Philippe Coussy

8 (Africa, Europe, Middle East)

Biography

Philippe Coussy is a full professor in the Lab-STICC (CNRS) at the Université de Bretagne-Sud, France, where he leads the “Design of Advanced Architectures” group. He was graduated from Université Pierre et Marie Curie (MSc, 1999), Université de Bretagne-Sud (Ph.D., 2003 and Habilitation 2011). He holds the scientific excellence fellowship (PEDR/PES A) since 2008. He is member of the Advisory Board of the GDR on SoC-SIP and chair of the topic “embedded software and hardware architecture” since 2011. He is member of the Advisory Board of the GDR on BioComp and chair of the topic “system design” since 2015. He is a member of the technical committee of the IEEE Signal Processing Society, Design and Implementation of Signal Processing Systems (DISPS) since 2011. He is member of the European Network of Excellence HiPEAC. His research interests include system-level design and methodologies, high-level synthesis, computer-aided design for SoCs, embedded systems, low-power design for FPGAs and neuromorphic computing. He has supervised 16 PhD theses (5 in progress), 16 M.Sc. theses and published more than 60 papers in edited books, journals or conference proceedings on these topics. He holds 5 patents in hardware design domain. He has organized several workshops and tutorials in many outstanding international conferences including DAC, DATE, CODES+ISSS and ASP-DAC. He was guest editor for a special issue of Journal of Electrical and Computer Engineering on “ESL Design Methodology” (2012), guest editor for a special issue of IEEE Design and Test of Computer on “High-Level Synthesis” (2009) and co-editor of the books “High-Level Synthesis: From Algorithm to Digital Circuit” (Springer) (2008) and “Advanced Hardware Design for Error Correcting Codes” (Springer) (2014). He has been a member of the 2009 Catrene EDA roadmap and the 2011 HiPEAC roadmap committees. He regularly serves as a national expert (ANR, MESR) and international expert (Canada, Israel, Portugal…) participates as PC member in many international ACM/IEEE conferences (DATE, ICASSP, ISCAS, ASAP, GLSVLSI, SIPS, DAC, FPL…) and as reviewer for major journals (IEEE TCAD, TECS, JETCAS, D&T of Computers, ACM TODAES, TECS…). He is Associate Editor of the IEEE Signal Processing Letters for the Design and Implementation of signal processing systems (HWD-ARCH), Programmable Hardware e.g. FPGA, SoC or ASIC for DSP Algorithms (HDW-PROG) and Multicore Processors for DSP Algorithms (HDW-MCORE).

Affiliation(s)

Université de Bretagne-Sud

France

Zhiru Zhang

Cornell University

United States

Machine Learning/AI Automation

Peter A. Beerel

University of Southern California

United States

6 (Western U.S.)

Peter A. Beerel

6 (Western U.S.)

Biography

Peter Beerel received his B.S.E. degree in Electrical Engineering from Princeton University in 1989, and his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1991 and 1994, respectively. He joined the Department of Electrical Engineering-Systems at the University of Southern California's Viterbi School of Engineering in 1994, where he is currently a Full Professor. Dr. Beerel was the Faculty Director of Innovation Studies at the USC Stevens Institute for Innovation from 2006 to 2008. In May of 2008, he took a leave of absence from USC and co-founded TimeLess Design Automation with one of his Ph.D. students, Dr. Georgios Dimou. Their mission was to demonstrate and commercialize an asynchronous ASIC flow for high-performance systems. They were successful and sold the company in July of 2010 to Fulcrum Microsystems which was acquired by Intel in 2011. In 2015, his Ph.D. student, Dylan Hand, co-founded a second company, Reduced Energy Microsystems, to commercialize an asynchronous ASIC flow for ultra-low-power vision and machine learning systems. Dr. Beerel joined REM as Chief Scientist in 2016.

Dr. Beerel's research interests include a variety of topics in CAD and asynchronous VLSI design. He has been a member of the technical program committee for the International Symposium on Advanced Research in Asynchronous Circuits and Systems since 1997, was program co-chair for ASYNC'98, and was general co-chair for ASYNC'07. Dr. Beerel was recipient of a VSoE Outstanding Teaching Award in 1997 and the VSoE Junior Research Award in 1998. He received a National Science Foundation CAREER Award and a 1995 Zumberge Fellowship. He was also co-winner of the Charles E. Molnar award for two papers published in ASYNC'97 that best bridged theory and practice of asynchronous system design, was co-recipient of the best paper award in ASYNC'99, and winner of the best paper award in ASYNC'2014. He was the 2008 recipient of the IEEE Region 6 Outstanding Engineer Award for significantly advancing the application of asynchronous circuits to modern VLSI chips.

Affiliation(s)

University of Southern California

United States

Muhammad Shafique

New York University Abu Dhabi

United Arab Emirates

8 (Africa, Europe, Middle East)

Li-C Wang

University of California, Santa Barbara

United States

6 (Western U.S.)

Massimo Poncino

Politecnico di Torino

Italy

8 (Africa, Europe, Middle East)

Xue (Shelley) Lin

Northeastern University

United States

4 (Central U.S.)

Mohamed M Sabry

NTU

Singapore

10 (Asia and Pacific)

Theo Theocharides

University of Cyprus

Cyprus

10 (Asia and Pacific)

Theo Theocharides

10 (Asia and Pacific)

Biography

I am an Associate Professor in the Electrical and Computer Engineering Department, of the University of Cyprus.

My research revolves around the design of reliable and low power embedded and application-specific processors, media and computer vision hardware architectures and real-time digital artificial intelligence applications, geared towards edge-based, resource-constrained scenarios. My main interests lie in the fields of vision for autonomous terrestrial and aerial robotics (drones), and acceleration of deep learning algorithms for IoT applications such as distributed sensor networks, wearable sensors, smart infrastructures, etc. Furthermore, I am interested in acceleration of big data applications such as bioinformatics (proteomics and genomics) using heterogeneous computing platforms and reconfigurable hardware.

I am the director of the Embedded and Application Specific Systems-on-Chip Laboratory, and a faculty member and Director of Research of the KIOS Research and Innovation Center of Excellence. My lab's current research focuses on the development of low-power and reliable on-chip application-specific architectures, low-power VLSI design, embedded systems design and exploration of energy-reliability trade-offs for Systems on Chip and Embedded Systems. Our focus lies on acceleration of computer vision and artificial intelligence algorithms in hardware and low-power embedded processors suitable for edge intelligence, and in utilizing reconfigurable hardware towards self-aware, evolvable computing systems. Our research interests span also across the emerging areas of evolvable hardware design, and perceptual computing.

I serve on several organizing and technical program committees of various conferences, and I am a Senior Member of the IEEE, a member of the ACM, and an Associate Editor for IEEE Consumer Electronics magazine and the ETRI Journal. I also serve on the Editorial Boards of IEEE Design & Test magazine, and ACM Transactions on Embedded Computing Systems.

I am currently the editor of the Test Technology Technical Council newsletter for the IEEE Design & Test of Computers, for which I also serve as the Information Editor. I am also editing the newsletter for the Journal of Electronic Testing. If you wish to submit a TTTC-sponsored event for publication into an upcoming IEEE D&T or JETTA, please email me with the details.

Affiliation(s)

University of Cyprus

Cyprus

Niraj K. Jha

Princeton University

United States

1 (Northeastern U.S.)

Niraj K. Jha

1 (Northeastern U.S.)

Biography

Niraj K. Jha (S’85-M’85-SM’93-F’98) received the BTech degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 1981, the MS degree in electrical engineering from S.U.N.Y. at Stony Brook, New York, in 1982, and the PhD degree in electrical engineering from the University of Illinois at Urbana-Champaign, Illinois, in 1985.

He is a professor of electrical engineering with Princeton University. He received the Distinguished Alumnus Award from I.I.T., Kharagpur in 2014. He is a recipient of the AT&T Foundation Award, NEC Preceptorship Award for research excellence, NCR Award for teaching excellence, six School of Engineering and Applied Sciences Teaching Commendations, and Princeton University Graduate Mentoring Award.

He has served as the editor-in-chief of the IEEE Transactions on VLSI Systems and an associate editor of the IEEE Transactions on Circuits and Systems I and II, the IEEE Transactions on VLSI Systems, the IEEE Transactions on Computer-Aided Design, the IEEE Transactions on Computers, the Journal of Electronic Testing: Theory and Applications, and the Journal of Nanotechnology. He is currently serving as an associate editor of the IEEE Transactions on Multi-Scale Computing Systems and the Journal of Low Power Electronics. He has served as the program chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004 International Conference on Embedded and Ubiquitous Computing, and the 2010 International Conference on VLSI Design, as the director of the Center for Embedded System-on-a-chip Design funded by New Jersey Commission on Science and Technology, as the associate director of the Andlinger Center on Energy and the Environment, and on the program committees of more than 170 conferences and workshops. His research interests include embedded computing, secure computing, machine learning, monolithic 3D IC design, low power hardware/software design, and computer-aided design of integrated circuits and systems. He has given several keynote speeches in the areas of nanoelectronic design/test and embedded systems. He is a fellow of the IEEE and ACM

Affiliation(s)

Princeton University

United States

Modeling & Simulation

Chung-Kuan Cheng

University of California, San Diego

United States

6 (Western U.S.)

Eric Keiter

Sandia National Laboratories

United States

6 (Western U.S.)

Wenjian Yu

Tsinghua University

China

10 (Asia and Pacific)

Cristell Maneux

University of Bordeaux

France

8 (Africa, Europe, Middle East)

Physical Design

Laleh Behjat

University of Calgary

Canada

7 (Canada)

Iris Hui-Ru Jiang

National Taiwan University

Taiwan

10 (Asia and Pacific)

Iris Hui-Ru Jiang

10 (Asia and Pacific)

Biography

Iris Hui-Ru Jiang received the B.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan. She has been with National Chiao Tung University, Hsinchu, Taiwan, from 2005 to 2017. She is currently a Professor with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan. She has been a Visiting Scholar with IBM Austin Research Laboratory, Austin, TX, USA, from 2013 to 2014. Her current research interests include physical design optimization, interaction between logic design and physical synthesis, timing analysis and optimization, design for manufacturability, and data analytics-based design automation.

Dr. Jiang was a recipient of the Best Paper Award Nomination from Design Automation Conference (DAC) 2016 and International Symposium on Physical Design (ISPD) 2013, the Best in-track Paper Award from International Conference on Computed Aided Design (ICCAD) 2014, the 2011 Outstanding Young Electrical Engineer Award and 2018 Outstanding Electrical Engineering Professor Award from Chinese Institute of Electrical Engineering. She and her students were the recipients of the First Place Award at the CAD Contest at ICCAD in 2012, two Third Place Awards at the TAU Timing Analysis Contests in 2013 and 2014, four First Place Awards at the TAU Timing Analysis Contest in 2015, 2017, 2018, and 2019.

She is currently the Chair of IEEE CEDA Design Automation Technical Committee and has organized CAD contest at ICCAD from 2012 to 2014 and [email protected], since 2016. She is currently an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and has served on technical program committees of major EDA conferences, including DAC, ICCAD, ISPD, etc. She is a member of the Phi Tau Phi Scholastic Honor Society.

Affiliation(s)

National Taiwan University

Taiwan

David Pan

University of Texas at Austin

United States

5 (Southwestern U.S.)

David Pan

5 (Southwestern U.S.)

Biography

David Z. Pan is a Professor and holder of Silicon Laboratories Endowed Chair at the Department of Electrical and Computer Engineering, The University of Texas at Austin. His research interests include bidirectional AI and IC interactions, electronic design automation, design for manufacturing, hardware security, and CAD for analog/mixed-signal ICs and emerging technologies. He has published over 400 refereed journal/conference papers and 8 US patents. He has served in many journal editorial boards and conference committees, including various leadership roles such as ICCAD 2019 General Chair, ASP-DAC 2017 TPC Chair, and ISPD 2008 General Chair. He has received many awards, including SRC Technical Excellence Award, 19 Best Paper Awards (ISPD 2020, ASP-DAC 2020, DAC 2019, GLSVLSI 2018, VLSI Integration 2018, HOST 2017, SPIE 2016, ISPD 2014, ICCAD 2013, ASP-DAC 2012, ISPD 2011, IBM Research 2010 Pat Goldberg Memorial Best Paper Award in CS/EE/Math, ASP-DAC 2010, DATE 2009, ICICDT 2009, SRC Techcon in 1998, 2007, 2012 and 2015), DAC Top 10 Author Award in Fifth Decade, ASP-DAC Frequently Cited Author Award, Communications of ACM Research Highlights, ACM/SIGDA Outstanding New Faculty Award, NSF CAREER Award, IBM Faculty Award (4 times), and many international CAD contest awards. He has graduated 35 Ph.D. students who have won many awards, including First Place of ACM Student Research Competition Grand Finals (twice, in 2018 and 2021), ACM/SIGDA Student Research Competition Gold Medal (x3), ACM Outstanding Ph.D. Dissertation in EDA Award (x2), and EDAA Outstanding Dissertation Award (x2). He is a Fellow of IEEE and SPIE.

Affiliation(s)

University of Texas at Austin

United States

Secure, Reliable Systems

Yanjing Li

University of Chicago

United States

4 (Central U.S.)

James Chien-Mo Li

National Taiwan University

Taiwan

10 (Asia and Pacific)

Synthesis and Verification

Luca G. Amaru

Synopsys, Inc.

United States

6 (Western U.S.)

Sicun Gao

University of California, San Diego

United States

6 (Western U.S.)

Hao Zheng

University of South Florida

United States

3 (Southeastern U.S.)

Weikang Qian

Shanghai Jiao Tong University

10 (Asia and Pacific)

System-Level Design

Luca Carloni

Columbia University

United States

1 (Northeastern U.S.)

Cristiana Bolchini

Politecnico di Milano

Italy

8 (Africa, Europe, Middle East)

Yu Wang

Tsinghua University

China

10 (Asia and Pacific)

Marina Zapater

University of Applied Sciences Western Switzerland (HES-SO)

Switzerland

8 (Africa, Europe, Middle East)

Weichen Liu

Nanyang Technological University

Singapore

10 (Asia and Pacific)

Test

Anne Gattiker

IBM Research, Austin

United States

5 (Southwestern U.S.)

Xiaowei Li

Chinese Academy of Sciences (CAS)

China

10 (Asia and Pacific)

Xiaowei Li

10 (Asia and Pacific)

Biography

Xiaowei Li (SM'04) received the BEng and MEng degrees in computer science from the Hefei University of Technology, Hefei, China, in 1985 and 1988, respectively, and the PhD degree in computer science from the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), Beijing, China, in 1991. He was an associate professor with the Department of Computer Science and Technology, Peking University, Beijing, from 1991 to 2000. In 2000, he joined ICT, CAS, as a professor, where he is currently the deputy director of the State Key Laboratory of Computer Architecture. He has co-authored more than 280 papers in journals and international conferences, and he holds 60 patents and 30 software copyrights. His current research interests include VLSI testing, design for testability, design verification, dependable computing, and wireless sensor networks. He has been the vice-chair of the IEEE Asia & Pacific Regional Test Technology Technical Council (TTTC) since 2004. He is currently vice-chair of IEEE TTTC. He was the chair of the Technical Committee on Fault Tolerant Computing, China Computer Federation (2008-2012), and Steering Committee chair of IEEE Asian Test Symposium (2011-2013). He was Steering Committee Chair of IEEE Workshop on RTL and High Level Testing (2007-2010). He services as associate editor of the Journal of Computer Science and Technology, the Journal of Low Power Electronics, JETTA and TCAD. He is a senior member of the IEEE.

Affiliation(s)

Chinese Academy of Sciences (CAS)

China

Giorgio Di Natale

CNRS/TIMA

France

8 (Africa, Europe, Middle East)

Jennifer Dworak

Southern Methodist University

United States

TCAD Editor-at-Large Board

Sharad Malik

Princeton University

United States

1 (Northeastern U.S.)

Sharad Malik

1 (Northeastern U.S.)

Biography

Sharad Malik (F’02) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India, in 1985, and the M.S. and Ph.D. degrees in computer science from the University of California at Berkeley, Berkeley, CA, USA, in 1987 and 1990, respectively.

He served as the Director of the Keller Center for Innovation in Engineering Education, Princeton University, Princeton, NJ, USA, from 2006 to 2011. He is the George Van Ness Lothrop Professor of Engineering with Princeton University and the Chair of the Department of Electrical Engineering. He has served as the Director of the multi-university MARCO Gigascale Systems Research Center, Berkeley, CA, USA, from 2009 to 2012, and as the Associate Director of the Center for Future Architectures Research, Ann Arbor, MI, USA, from 2013 to 2016. His research in functional timing analysis and propositional satisfiability has been widely used in industrial electronic design automation tools. His current research interest includes design methodology and design automation for computing systems.

Dr. Malik has received the IEEE/ACM Design Automation Conference Award for the most cited paper in the 50-year history of the conference in 2013, the Computer-Aided Verification Award for fundamental contributions to the development of high-performance Boolean satisfiability solvers in 2009, the IEEE/ACM International Conference on Computer-Aided Design Ten Year Retrospective Most Influential Paper Award in 2011, the IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation in 2017, the Princeton University Presidents Award for Distinguished Teaching in 2009, the IIT Delhi Distinguished Alumni Award in 2009, as well as several other research and teaching awards. He is a fellow of the ACM.

Affiliation(s)

Princeton University

United States

Sachin Sapatnekar

University of Minnesota

United States

4 (Central U.S.)

Website

Sachin Sapatnekar

4 (Central U.S.)

Website

Biography

Sachin Sapatnekar received the B. Tech. degree from the Indian Institute of Technology, Bombay in 1987, the M. S. degree from Syracuse University in 1989, and the Ph. D. degree from the University of Illinois at Urbana-Champaign in 1992. He worked at Texas Instruments during the summer of 1990, and at Intel Corporation during the summer of 1997. His other major educational qualifications include self-taught basic juggling under the long-distance tutelage of the world-renowned Klutz School in 1991, and the PADI Open Water Diver Certification from Deep Sea Divers Den in 2001. With his once-a-decade average of trying something new, he is sure to remain his same old boring self until 2011. So boring that it's well past 2011, and this hasn't been updated.

He was an Assistant Professor in the Department of Electrical and Computer Engineering at Iowa State University from 1992 to 1997. He is currently a Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, where he holds the Robert and Marjorie Henle chair and the Distinguished McKnight University Professorship. His current research interests lie in developing efficient techniques for computer-aided design of integrated circuits and are primarily centered around physical design, timing and simulation issues, and optimization algorithms. He has served on the editorial boards of several IEEE journals, including as Editor-in-Chief of the IEEE Transactions on CAD. He was a Technical Program Co-chair in 2006 and 2007 for the Design Automation Conference (DAC), and the General Chair in 2010. He has also been the Technical Program Chair and General Chair for the International Symposium on Physical Design (ISPD) and the Tau workshop, and Program Chair for the International Conference on VLSI Design in India. He is a recipient of the NSF Career Award, the SRC Technical Excellence Award, the SIA University Researcher Award, Best Paper Awards at the DAC'97, ICCD'98, DAC'01 DAC'03, ISPD'09, ISQED'10, and ASYNC'16 conferences, a Best Poster Award at IRPS'12, and the ICCAD Ten-Year Retrospective Most Influential Paper Award in 2013 and 2016. He has been a Fulbright Senior Researcher at Universitat Politècnica de Catalunya in Barcelona in 2013, and a DJ Gandhi Visiting Professor at the Indian Institute of Technology, Bombay in 2014. He is a Fellow of the IEEE (2003) and the ACM (2016).

Affiliation(s)

University of Minnesota

United States

Alberto Sangiovanni-Vincentelli

University of California, Berkeley

United States

6 (Western U.S.)

Alberto Sangiovanni-Vincentelli

6 (Western U.S.)

Biography

Alberto Sangiovanni Vincentelli is the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Sciences at the University of California at Berkeley. In 1980-1981, he was a Visiting Scientist at the Mathematical Sciences Department of the IBM T.J. Watson Research Center. In 1987, he was Visiting Professor at MIT. He is an author of over 800 papers, 17 books and 2 patents in the area of design tools and methodologies, large scale systems, embedded systems, hybrid systems and innovation. He was a co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation and the founder and Scientific Director of the PARADES Research Center in Rome.

Board Participation: • Public Companies: He has been a member of the Board of Directors of Cadence and of KPIT-Cummins. • Privately Held Companies: He is a member of the Board of Directors of Sonics, and of Expert Systems. • Advisory Boards: He had been a member of the ST microelectronics Advisory Board for 10 years. He was a member of the HP Strategic Technology Advisory Board (2005-2007), a member of the Science and Technology Advisory Board of General Motors (2003-2013), and is a member of the Technology Advisory Council of United Technologies Corporation (2005-present). He is a member of the Advisory Board of Innogest, Xseed and a member of the Investment Committee of Atlante Ventures and Fondo Next. Since January 2013, he is the President of the Strategic Committee of the Italian Strategic Fund. He is member of the Scientific Council of the Italian National Science Foundation (CNR). Since February 2010, he has been a member of the Executive Committee of the Italian Institute of Technology. Since July 2012, he has been named Chairperson of the Comitato Nazionale Garanti per la Ricerca.

Affiliation(s)

University of California, Berkeley

United States

Li-Shiuan Peh

NUS

Singapore

10 (Asia and Pacific)

Donatella Sciuto

Politecnico di Milano

Italy

8 (Africa, Europe, Middle East)

Ingrid Verbauwhede

KUL

Belgium

8 (Africa, Europe, Middle East)