TCAD Editorial Board | IEEE Council on Electronic Design Automation

TCAD Editor-in-Chief

Rajesh K. Gupta

University of California, San Diego

United States

6 (Western U.S.)

Rajesh K. Gupta

6 (Western U.S.)

Biography

Rajesh K. Gupta (F’91) received the B.Tech. degree in electrical engineering from Indian Institute of Technology Kanpur, Kanpur, India, in 1984, the M.S. degree in EECS from University of California, Berkeley, Berkeley, CA, USA, in 1986, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, USA, in 1994.

He is a Qualcomm Endowed Chair Professor with the Department of Computer Science and Engineering, University of California, San Diego, San Diego, CA, USA. He was a Circuit Designer with Intel Corporation, Santa Clara, CA, USA, as a member of three successful processor design teams and on the Computer Science Faculty, University of Illinois, Urbana-Champaign, Champaign, IL, USA and the University of California, Irvine, Irvine, CA, USA. Regardless of the title, the focus of the research has been on methods and tools to make things better, such as, more energy-efficient and reliable, or enable others (mostly, designers and architects) to do things better. To the extent a problem area requires it, there is a focus on creating usable artifacts or at least find the limits on what is achievable in practice. His past contributions include SystemC modeling and SPARK parallelizing high-level synthesis, both of which have been incorporated into industrial practice. His publications and patents cover various aspects of embedded systems design, design automation, clock design, data-path synthesis, system-on-chip modeling, and dynamic power management. He was a Lead or a Co-Lead of DARPA-sponsored efforts under the data-intensive systems and power-aware computing and communications programs on the role of adaptation in energy-efficient system architectures. His ongoing projects are focused on efficient compositional synthesis of system-chips, microelectronic variability, accurate timing, and synchronization for the integrated systems. His current research interests include embedded,cyber-physical systems, and Internet-of-Things.

Dr. Gupta was a recipient of the Best Demonstration Paper Award at ACM BuildSys’16, the Best Paper Award at IEEE/ACM DCOSS’08, and the Best Demonstration Award at IEEE/ACM IPSN/SPOTS’05 with and his students. He is a fellow of the ACM.

Affiliation(s)

University of California, San Diego

United States

TCAD Deputy EiC

Xin Li

Duke University

United States

3 (Southeastern U.S.)

Xin Li

3 (Southeastern U.S.)

Biography

Prof. Xin Li received the Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, Pennsylvania, in 2005, and the M.S. and B.S. degrees in Electronics Engineering from Fudan University, Shanghai, China, in 2001 and 1998, respectively.

In 2005, he co-founded Xigmix Inc. to commercialize his PhD research, and served as the Chief Technical Officer until the company was acquired by Extreme DA in 2007. In 2011, Extreme DA was further acquired by Synopsis (Nasdaq: SNPS). From 2009 to 2012, he was the Assistant Director for FCRP Focus Research Center for Circuit & System Solutions (C2S2), a national consortium of 13 research universities (CMU, MIT, Stanford, Berkeley, UIUC, UMich, Columbia, UCLA, among others) chartered by the U.S. semiconductor industry and U.S. Department of Defense to work on next-generation integrated circuit design challenges. From 2014 to 2015, he was the Assistant Director for the Center for Silicon System Implementation (CSSI), a CMU research center with 20 faculty members working on integrated circuits and systems. His research interests include integrated circuit, signal processing and data analytics.

He was an Associate Editor of IEEE Trans. on Biomedical Engineering (TBME), IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), ACM Trans. on Design Automation of Electronic Systems (TODAES), IEEE Design & Test (D&T), and Journal of Low Power Electronics (JOLPE). He was the Guest Editor for IEEE TCAD, IEEE TNANO, IEEE TBD, IEEE D&T, IEEE JETCAS, ACM TCPS, ACM JETC and VLSI Integration. He served on the Executive Committee of ACM Special Interest Group on Design Automation (SIGDA), IEEE Systems, Man, and Cybernetics Society Technical Committee on Cybernetics for Cyber-Physical Systems (TCCCPS), and IEEE Computer Society Technical Committee on VLSI (TCVLSI). He was the General Chair of ISVLSI, iNIS and FAC, and the Technical Program Chair of CAD/Graphics. He also served on the ACM/SIGDA Outstanding PhD Dissertation Award Selection Committee, the IEEE TTTC E. J. McCluskey Best Doctoral Thesis Selection Committee, the IEEE Outstanding Young Author Award Selection Committee, the Executive Committee of ISVLSI, GLSVLSI and iNIS, and the Technical Program Committee of DAC, ICCAD, ITC, ISVLSI, FAC, CAD/Graphics, ASICON and VLSI. He received the NSF Faculty Early Career Development Award (CAREER) in 2012, two IEEE Donald O. Pederson Best Paper Awards in 2013 and 2016, the Best Paper Award from Design Automation Conference (DAC) in 2010, two IEEE/ACM William J. McCalla ICCAD Best Paper Awards in 2004 and 2011, and the Best Paper Award from International Symposium on Integrated Circuits (ISIC) in 2014. In addition to these awards, he also received six Best Paper Nominations from Design Automation Conference (DAC), International Conference on Computer-Aided Design (ICCAD) and Custom Integrated Circuits Conference (CICC).

Affiliation(s)

Duke University

United States

TCAD Managing Editor

Sara Dailey

Dailey EAS, LLC

United States

4 (Central U.S.)

TCAD Webmaster

Ing-Chao Lin

National Cheng Kung University

Taiwan

10 (Asia and Pacific)

TCAD Associate Editors

Analog & Mixed Signal

Fabrizio Bonani

Politecnico di Torino

Italy

8 (Africa, Europe, Middle East)

Saraju P. Mohanty

University of North Texas

United States

5 (Southwestern U.S.)

Saraju P. Mohanty

5 (Southwestern U.S.)

Biography

Dr. Saraju P. Mohanty is a Professor in the Department of Computer Science and Engineering (CSE), University of North Texas (UNT), Denton, TX; a Tier-One (R1) Research University as per Carnegie Classification, where he directs the Smart Electronic Systems Laboratory (SESL). He received IEEE Consumer Electronics Society Outstanding Service Award in 2020 for leadership contributions to the IEEE Consumer Electronics society. He received IEEE-CS-TCVLSI Distinguished Leadership Award in 2018 for services to the IEEE, and to the VLSI research community. He has been recognized as a IEEE Distinguished Lecturer by the Consumer Electronics Society (CESoc) during 2017-2018. He was conferred the Glorious India Award in 2017 for his exemplary contributions to the discipline. He received Society for Technical Communication (STC) 2017 Award of Merit for his outstanding contributions to IEEE Consumer Electronics Magazine. He was the recipient of 2016 PROSE Award for best Textbook in Physical Sciences & Mathematics category from the Association of American Publishers (AAP) for his book titled "Nanoelectronic Mixed-Signal System Design" published by McGraw-Hill in 2015. He was conferred 2016-17 UNT Toulouse Scholars Award for sustained excellent scholarship and teaching achievements. Prof. Mohanty's research is in "Smart Electronic Systems". Prof. Mohanty's research has been funded by many agencies including the National Science Foundation (NSF), the Semiconductor Research Corporation (SRC), the US Air Force, the IUSSTF, and the Mission Innovation. Dr. Mohanty is an inventor of 4 US patents. Prof. Mohanty is an author of 300 peer-reviewed articles and 4 books. His Google Scholar h-index is 35 and i10-index is 126 with 5000+ citations. He has received 11 best paper awards. He has delivered 9 keynotes and served on 5 panels at various International Conferences.

Prof. Mohanty has been serving on the Board of Governors (BoG) of the IEEE Consumer Electronics Society. Prof. Mohanty has been serving on the editorial board of several peer-reviewed international transactions/journals, including IEEE Transactions on Consumer Electronics (TCE), IEEE Transactions on Big Data (TBD), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), and ACM Journal on Emerging Technologies in Computing Systems (JETC). He is currently the Editor-in-Chief (EiC) of the IEEE Consumer Electronics Magazine (CEM). He served as a founding Editor-in-Chief (EiC) of the VLSI Circuits and Systems Letter (VCAL) during 2015-2018. Prof. Mohanty served as the Chair of Technical Committee on Very Large Scale Integration (TCVLSI), IEEE Computer Society (IEEE-CS) during 2014-2018 to oversee a dozen of IEEE conferences. He serves on the steering, organizing, and program committees of several international conferences. He is the founding steering committee chair for the IEEE International Symposium on Smart Electronic Systems (iSES), steering committee vice-chair of the IEEE-CS Symposium on VLSI (ISVLSI), and steering committee vice-chair of the OITS International Conference on Information Technology (ICIT). Prof. Mohanty is the Conference Chair of ICCE 2018, the flagship Conference of IEEE CE Society, which is co-located with International Consumer Electronics Show (CES) as its research/education component; CES is the world's largest CE show with 3,800 exhibiting companies, 300 conference sessions and more than 165,000 attendees from 150 countries.

Prof. Mohanty has supervised 11 Ph.D. dissertations and 26 M.S. theses. Ten of his advisees have received outstanding students/alumni awards at UNT. The students are very well placed in the industry and academia. He has received Honors Day recognition as an inspirational faculty at UNT for multiple years. He has also received UNT Provost’s Thank a Teacher recognition for multiple years.

Prof. Mohanty obtained a Ph.D. in Computer Science and Engineering (CSE) in 2003, from the University of South Florida (USF), Tampa, a top-tier institution that ranks among the top Universities in the USA and the world. His Masters degree in Systems Science and Automation (currently rebranded as Masters in Artificial Intelligence) is from the highest ranked research institute from India, the Indian Institute of Science (IISc), Bengaluru, in 1999. He obtained a Bachelors degree with Honors in Electrical Engineering from the top-ranked Government Engineering College of the state of Odisha, the College of Engineering and Technology at Bhubaneswar (CETB), Orissa University of Agriculture and Technology (OUAT), Bhubaneswar, India, in 1995. He is considered a notable alumnus of all the schools that he attended for his undegraduate and graduate studies. He was conferred with the President’s Scout Award by the Honorable President of India in 1988.

Affiliation(s)

University of North Texas

United States

Peng Li

University of California, Santa Barbara

United States

6 (Western U.S.)

Peng Li

6 (Western U.S.)

Biography

I received the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA in 2003 and the M. Eng. degree in systems engineering and B.Eng. degree in information science & engineering from Xi’an Jiaotong University, Xi’an, China, in 1997 and 1994, respectively.

I have been a Professor of ECE at UCSB since July 2019, where I'm affiliated with the Computer Engineering (CE) Program. From August 2004 to June 2019, I was with the Department of Electrical and Computer Engineering at Texas A&M University as an assistant, associate, and then a full professor. I was was a member of Faculty of Neuroscience and the Graduate Faculty of School of Graduate Studies, Health Science Center at Texas A&M.

My research interests are in integrated circuits and systems, learning algorithms and circuits for neuromorphic (a.k.a brain-inspired) computing, VLSI computer-aided design, machine learning and its hardware realization in VLSI, and computational brain modeling. I am a co-editor of the book, entitled "Simulation and Verification of Electronic and Biological Systems" (Springer, 2011), co-edited one additional book, and authored and co-authored over 200 journal and conference publications, and seven book chapters.

My work has been recognized by various distinctions including the ICCAD Ten Year Retrospective Most Influential Paper Award in 2019, four IEEE/ACM Design Automation Conference (DAC) Best Paper Awards in 2003, 2008, 2011, and 2016, the ISCAS Honorary Mention Best Paper Award from the Neural Systems and Applications Technical Committee of IEEE Circuits and Systems (CAS) Society at IEEE International Symposium on Circuits and Systems (ISCAS) in 2016, the IEEE/ACM William J. McCalla ICCAD Best Paper Award from IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2012, the US National Science Foundation CAREER Award in 2008, two Inventor Recognition Awards from Microelectronics Advanced Research Corporation (MARCO) in 2006 and 2007, two Semiconductor Research Corporation (SRC) Inventor Recognition Awards in 2001 and 2004. At the 50th IEEE/ACM Design Automation Conference in 2013, I was honored with the Best Paper Hat Trick Award for receiving the prestigious DAC best paper award three times, the DAC Prolific Author Award, and the DAC Top 10 Author in Fifth Decade Award. I recieved several Best Paper Award nominations from ICCAD. At Texas A&M, I was recongnized with the 2018-2019 Eugene E. Webb Faculty Fellow, 2013-2014 William and Montine P. Head Fellow, 2011-2012 TEES Fellow Award from the College of Engineering, and the ECE Outstanding Professor Award in 2008.

I was an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems from 2008 to 2013 and an associate editor for IEEE Transactions on Circuits and Systems II from 2008 to 2016. I have been on the committees of many international conferences and workshops such as DAC, ISLPED, IJCNN, ICCAD, ICCD, ISQED, ISCAS, TAU and FAC, ICCAD Best Paper Award Committee, and the selection committee for ACM Outstanding Ph.D. Dissertation Award in Electronic Design Automation. He served as the technical program committee chair for the ACM TAU Workshop in 2009 and general chair for the 2010 Workshop. I was a member of the Executive Committee and the Vice President for Technical Activities of IEEE Council on Electronic Design Automation (CEDA) from Jan. 2016 to Dec. 2017.

I have consulted for Intel Corporation and several Silicon-Valley startup companies. I am a Fellow of the IEEE and a member of the ACM.

Affiliation(s)

University of California, Santa Barbara

United States

Approximate Computing

Xun Jiao

Villanova University

United States

2 (Eastern U.S.)

Gang Qu

University of Maryland

United States

2 (Eastern U.S.)

Sherief Reda

Brown University

United States

1 (Northeastern U.S.)

Architectural Design & Optimization

Luca Benini

Università di Bologna

Italy

8 (Africa, Europe, Middle East)

Luca Benini

8 (Africa, Europe, Middle East)

Biography

Prof. Luca Benini is the chair of digital Circuits and Systems at D-ITET ETHZ.
He received a Ph.D. degree in electrical engineering from Stanford University in 1997.

He has served as Chief Architect for the Platform2012/STHORM project in STMicroelectronics, Grenoble in the period 2009-2013. He is also a professor at the University of Bologna and has held visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford University.

Dr. Benini's research interests are in the design of energy-efficient digital systems with special emphasis on ultra-low-power System-on-Chip and green HPC systems. He is also active in the area of smart sensors and sensor networks for consumer, biomedical and Internet-of-Things applications. In these areas, he has coordinated tens of funded projects, including an ERC Advanced Grant on Multiscale thermal management of Computing Systems.

He has been general chair of the Design Automation and Test in Europe Conference, of the Network on Chip Symposium and of the International Symposium on Low Power Electronics and Design. He is an Associate Editor of the IEEE Transactions on Computer-Aided Design of Circuits and Systems and the ACM Transactions on Embedded Computing Systems.

He has published more than 700 papers in peer-reviewed international journals and conferences, four books and several book chapters. He is a Fellow of the IEEE and the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg Award.

Affiliation(s)

Università di Bologna

Italy

Swiss Federal Institute of Technology, Zurich

Switzerland

Robert Wille

Johannes Kepler University

Austria

8 (Africa, Europe, Middle East)

Robert Wille

8 (Africa, Europe, Middle East)

Biography

From 2002 to 2006, Robert Wille studied Computer Science (Diploma) at the University of Bremen. After successfully completing his doctorate in 2009 (summa cum laude), he worked as a postdoc at the University of Bremen and, since 2013, as Senior Researcher in the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). Besides that, he served as a lecturer at the University of Applied Science Bremen from 2010 to 2012 and was a guest professor for Technical Computer Science at the University of Potsdam in 2012 as well as for Embedded Systems at the Technical University of Dresden in 2013/2014. In 2014, he completed his habilitation and, since October 2015, he is a full professor at the Johannes Kepler University Linz and head of the Institute for Integrated Circuits.

Robert Wille’s expertise is in the development of design technologies for various application areas – with a particular focus on the design, verification, and test of circuits and systems. He considers conventional as well as emerging computing technologies such as quantum computation, reversible circuits, or microfluidic biochips. Since 2007, Robert Wille published more than 200 journal and conference papers in this area (including top-notch venues such as DAC, DATE, ICCAD, ASP-DAC, MoDELS, or TCAD) and was repeatedly awarded (e.g. with a Google Research Award in 2018 as well as Best Paper Awards at the International Conference on Computer-Aided Design in 2013 and the Forum on Specification and Design Languages in 2010).

Robert Wille served as Associate Editor and Guest Editor for various renowned journals such as the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), the ACM Journal on Emerging Technologies in Computing Systems (JETC), or Springer’s Lecture Notes in Computer Science (LNCS). Additionally, he was General Chair and PC Chair at several conferences such as at the Forum on Description Languages, the Conference on Reversible Computation, and the International Symposium on Multiple-Valued Logic (ISMVL) as well as served as Subcommittee Chair at the Asia and South Pacific Design Automation Conference (ASP-DAC), was in program committees of numerous conferences such as ASP-DAC, DAC, DATE, ICCAD, ISMVL, etc., and organized several conferences, tutorials, Dagstuhl seminars, workshops, and special sessions.

Affiliation(s)

Johannes Kepler University

Austria

Automation for Emerging Technologies

Philip Brisk

University of California, Riverside

United States

6 (Western U.S.)

Suman Chakraborty

Indian Institute of Technology, Kharagpur

India

10 (Asia and Pacific)

Tsung-Yi Ho

National Tsing Hua University

Taiwan

10 (Asia and Pacific)

Tsung-Yi Ho

10 (Asia and Pacific)

Biography

Tsung-Yi Ho (SM’10) received the Ph.D. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2005. He is a Professor with the Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. He has presented ten tutorials and contributed 11 special sessions in ACM/IEEE conferences, all in design automation for microfluidic biochips. His research interests include design automation and test for microfluidic biochips and nanometer integrated circuits.

Dr. Ho is the recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science, the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, and the Hans Fischer Fellowship by the Institute of Advanced Study, Technical University of Munich. He was a recipient of the Best Paper Awards at the VLSI Test Symposium in 2013 and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2015. He served as a Distinguished Visitor of the IEEE Computer Society for 2013–2015, the Chair of the IEEE Computer Society Tainan Chapter for 2013–2015, and the Chair of the ACM SIGDA Taiwan Chapter for 2014–2015. He is currently an ACM Distinguished Speaker, a Distinguished Lecturer of the IEEE Circuits and Systems Society, and an Associate Editor for the ACM Journal on Emerging Technologies in Computing Systems, the ACM Transactions on Design Automation of Electronic Systems, the ACM Transactions on Embedded Computing Systems, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and the Technical Program Committees of major conferences, including the Design Automation Conference, the International Conference on Computer-Aided Design, the IEEE/ACM Design Automation and Test in Europe Conference, the Asia and South Pacific Design Automation Conference, the ACM/SIGDA International Symposium on Physical Design, and the International Conference on Computer Design.

Affiliation(s)

National Tsing Hua University

Taiwan

Design Automation for Cyber-Physical Systems & Internet of Things

Shiyan Hu

University of Southampton

United Kingdom

8 (Africa, Europe, Middle East)

Shiyan Hu

8 (Africa, Europe, Middle East)

Biography

Professor Shiyan Hu received his Ph.D. in Computer Engineering from Texas A&M University in 2008. Currently, he is a Professor (Chair in Cyber-Physical System Security) at University of Southampton. His research interests include Cyber-Physical Systems and Cyber-Physical System Security, where he has published more than 100 refereed papers, including 50+ in premier IEEE Transactions. He is an ACM Distinguished Speaker, an IEEE Systems Council Distinguished Lecturer, a recipient of the 2017 IEEE Computer Society TCSC Middle Career Researcher Award, and a recipient of the 2014 U.S. National Science Foundation (NSF) CAREER Award. His publications have received distinctions such as the 2018 IEEE Systems Journal Best Paper Award, the 2017 Keynote Paper in IEEE Transactions on Computer-Aided Design, the Front Cover Paper in IEEE Transactions on Nanobioscience in March 2014, Thomson Reuters ESI Highly Cited Paper 2017-2019, etc. His research has been featured in various public media such as National Science Foundation News Headlines, Science Daily, CBS, IEEE Spectrum, and Communications of ACM. He is the Chair for IEEE Technical Committee on Cyber-Physical Systems. He is the Editor-In-Chief of IET Cyber-Physical Systems: Theory & Applications. He is an Associate Editor for IEEE Transactions on Computer-Aided Design, IEEE Transactions on Industrial Informatics, IEEE Transactions on Circuits and Systems, ACM Transactions on Design Automation for Electronic Systems, and ACM Transactions on Cyber-Physical Systems. He is also a Guest Editor for eight IEEE/ACM journals such as Proceedings of the IEEE and IEEE Transactions on Computers. He has held chair positions in many conferences.

Affiliation(s)

University of Southampton

United Kingdom

Cyber-Physical Systems/Internet of Things

David Atienza

École Polytechnique Fédérale de Lausanne

Switzerland

8 (Africa, Europe, Middle East)

David Atienza

8 (Africa, Europe, Middle East)

Biography

David Atienza Alonso received his MSc and PhD degrees in Computer Science and Engineering from Complutense Univ. of Madrid (UCM), Spain, and IMEC, Belgium, in 2001 and 2005. Currently, he is an associate professor of electrical and computer engineering, and head of the Embedded Systems Laboratory (ESL) at the Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland. His research interests include system-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) and low-power Internet-of-Things (IoT) systems, including new 2-D/3-D thermal-aware design for MPSoCs and many-core servers, ultra-low power system architectures for wireless body sensor nodes and edge computing, HW/SW reconfigurable systems, dynamic memory optimizations, and network-on-chip design. He is a co-author of more than 250 publications in peer-reviewed international journals and conferences, several book chapters, and eight U.S. patents in these fields. He has earned several best paper awards and he is (or has been) an Associate Editor of IEEE TC, IEEE D&T, IEEE T-TCAD, IEEE T-SUSC and Elsevier Integration. He was the Technical Programme Chair of IEEE/ACM DATE 2015 and General Programme Chair of IEEE/ACM DATE 2017. Dr. Atienza received the DAC Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He is an IEEE Fellow and an ACM Distinguished Member.

Affiliation(s)

École Polytechnique Fédérale de Lausanne

Switzerland

Qi Zhu

Northwestern University

United States

4 (Central U.S.)

Qi Zhu

4 (Central U.S.)

Biography

Dr. Qi Zhu is a tenured Associate Professor in the Department of Electrical and Computer Engineering (ECE) at Northwestern University. He was an Assistant Professor and later Associate Professor in the ECE Department at University of California, Riverside from 2011 to 2017, and a Research Scientist at the Strategic CAD Labs in Intel from 2008 to 2011. Dr. Zhu received a Ph.D. in EECS from University of California, Berkeley in 2008, and a B.E. in CS from Tsinghua University in 2003. His research interests include model-based design, synthesis and verification of cyber-physical systems (CPS) and Internet of Things, CPS security, embedded and real-time systems, connected and autonomous vehicles, energy-efficient buildings and infrastructures, and system-on-chip design. He received best paper awards at Design Automation Conference (DAC) 2006, DAC 2007, International Conference on Cyber-Physical Systems (ICCPS) 2013, and ACM Transactions on Design Automation of Electronic Systems (TODAES) 2016. He received the NSF CAREER award in 2016, and the IEEE TCCPS (Technical Committee on Cyber-Physical Systems) Early-Career Award in 2017. Dr. Zhu is an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IET Cyber-Physical Systems: Theory & Applications, and IEEE TCCPS Newsletter. He served as an Associate Editor for IEEE TC-VLSI Newsletter and ACM SIGDA e-Newsletter, and as a Guest Editor for the Proceedings of the IEEE and ACM Transactions on Cyber-Physical Systems (TCPS). He is the Conference Chair of IEEE TCCPS. Dr. Zhu has served on the technical program committee and as organizer for a number of conferences in design automation, cyber-physical systems, embedded systems, and real-time systems, including DAC, ICCAD, DATE, ASP-DAC, ICCPS, CODES+ISSS, RTSS, RTAS, ICESS, GLVLSI, SAC, SIES, MEMOCODE, SAMOS, FDL, etc. He received the ACM SIGDA Service Award in 2015.

Affiliation(s)

Northwestern University

United States

3D Design & Optimization

Puneet Gupta

University of California, Los Angeles

United States

6 (Western U.S.)

Cheng Zhuo

Zhejiang University

China

10 (Asia and Pacific)

Cheng Zhuo

10 (Asia and Pacific)

Biography

Dr. Cheng Zhuo received B.S. degree from ChuKeChen College with major in Electrical Engineering and M.S. degree from Physical Electronics, in 2005 and 2007 respectively, in Zhejiang University. He received Ph.D degree in Computer Science & Engineering in 2010 from University of Michigan, Ann Abror. After graduation he joined Intel Corp., USA, in 2011 and led multiple research projects at Intel. In 2016, he joined Zhejiang University as a Professor and PhD Advisor. His current research interests include 3D integration, power and signal integrity, cyber physical system for medical applications, hardware accelorator and general VLSI EDA areas.

Dr. Zhuo has been invited to serve as an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE VLSI Circuits and Systems Letter, and Elsevier Integration, the VLSI Journal. He was a Guest editor for IET Cyber Physical System. He has also served in many technical program committees of top conferences in VLSI and EDA areas. He organized/co-organized ACM/SIGDA student research contest in 2017/2018, ISPD gate sizing contests in 2012/2013, SLIP 2105-2017, CSTIC 2018-2019, and special sessions in top conferences. He has been frequently invited as reviewers for international journals and conferences for VLSI design. He has published more than 60 peer-reviewed papers and coauthored 1 book chapter. He has received 4 Intel Division Recognition awards, 2012 ACM SIGDA technical leadership award, 2016 DAC Best Paper Nomination, 2017 JSPS Invitation Fellowship, 2018 CSTIC Best Student Paper Nomination, and 2018 DAC System Design Contest 2nd Place. He is a senior member of IEEE.

Affiliation(s)

Zhejiang University

China

Embedded Intelligence

Niraj K. Jha

Princeton University

United States

1 (Northeastern U.S.)

Niraj K. Jha

1 (Northeastern U.S.)

Biography

Niraj K. Jha (S’85-M’85-SM’93-F’98) received the BTech degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 1981, the MS degree in electrical engineering from S.U.N.Y. at Stony Brook, New York, in 1982, and the PhD degree in electrical engineering from the University of Illinois at Urbana-Champaign, Illinois, in 1985.

He is a professor of electrical engineering with Princeton University. He received the Distinguished Alumnus Award from I.I.T., Kharagpur in 2014. He is a recipient of the AT&T Foundation Award, NEC Preceptorship Award for research excellence, NCR Award for teaching excellence, six School of Engineering and Applied Sciences Teaching Commendations, and Princeton University Graduate Mentoring Award.

He has served as the editor-in-chief of the IEEE Transactions on VLSI Systems and an associate editor of the IEEE Transactions on Circuits and Systems I and II, the IEEE Transactions on VLSI Systems, the IEEE Transactions on Computer-Aided Design, the IEEE Transactions on Computers, the Journal of Electronic Testing: Theory and Applications, and the Journal of Nanotechnology. He is currently serving as an associate editor of the IEEE Transactions on Multi-Scale Computing Systems and the Journal of Low Power Electronics. He has served as the program chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004 International Conference on Embedded and Ubiquitous Computing, and the 2010 International Conference on VLSI Design, as the director of the Center for Embedded System-on-a-chip Design funded by New Jersey Commission on Science and Technology, as the associate director of the Andlinger Center on Energy and the Environment, and on the program committees of more than 170 conferences and workshops. His research interests include embedded computing, secure computing, machine learning, monolithic 3D IC design, low power hardware/software design, and computer-aided design of integrated circuits and systems. He has given several keynote speeches in the areas of nanoelectronic design/test and embedded systems. He is a fellow of the IEEE and ACM

Affiliation(s)

Princeton University

United States

Yiyu Shi

University of Notre Dame

United States

4 (Central U.S.)

Yiyu Shi

4 (Central U.S.)

Biography

Dr. Yiyu Shi is currently an associate professor in the Department of Computer Science and Engineering and Electrical Engineering (concurrent appointment) at the University of Notre Dame, the director of Sustainable Computing Lab (SCL), and the site director of the NSF Industry/University Cooperative Research Center (I/UCRC) on Alternative and Sustainable Intelligent Computing (ASIC). He was an August-Wilhelm Scheer visiting professor at Technical University of Munich in 2018, and an assistant professor in the Electrical and Computer Engineering Department at Missouri University of Science and Technology between 2010 and 2015, where he was the site co-director of the NSF I/UCRC on Net-Centric Software and Systems.

He received his B.S. degree (with honor) in Electronic Engineering from Tsinghua University, Beijing, China in 2005, the M.S (with honor) and Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2007 and 2009 respectively.

His current research interests include hardware intelligence and biomedical applications. In recognition of his research, many of his papers have been nominated for or awarded as the Best Paper in top conferences (DAC'05, ICCAD'07, ICCD'08, ASPDAC'09, DAC'09, ISPD'13, ICCAD'14, ISPD'15, DAC’16, DAC’19, CVPR Workshop’19, CODES+ISSS’19, ASPDAC’20). He was also the recipient of IBM Invention Achievement Award, Japan Society for the Promotion of Science (JSPS) Faculty Invitation Fellowship, Humboldt Research Fellowship, IEEE St. Louis Section Outstanding Educator Award, Academy of Science (St. Louis) Innovation Award, Missouri S&T Faculty Excellence Award, NSF CAREER Award, IEEE Region 5 Outstanding Individual Achievement Award, Air Force Summer Faculty Fellowship, and IEEE Computer Society TC-VLSI Mid-Career Award. He has served on the technical program committee of many international conferences including DAC, ICCAD, DATE, ISPD, ASPDAC and ICCD. He is an executive committee member of ACM SIGDA, a member of IEEE CEDA Publicity Committee, deputy editor-in-chief of IEEE VLSI CAS Newsletter, and an associate editor of IEEE TCAD, IEEE Access, ACM JETC, VLSI Integration, and IEEE TCCCPS Newsletter.

Affiliation(s)

University of Notre Dame

United States

Embedded Security

Rajat Subhra Chakraborty

Indian Institute of Technology, Kharagpur

India

10 (Asia and Pacific)

Swaroop Ghosh

Pennsylvania State University

United States

2 (Eastern U.S.)

Swaroop Ghosh

2 (Eastern U.S.)

Biography

Swaroop Ghosh received the B.E. (Hons.) from IIT, Roorkee, India, the M.S. degree from the University of Cincinnati, Cincinnati, and the Ph.D. degree from Purdue University, West Lafayette. He is an Assistant Professor at Penn State University. Earlier, he was with the faculty of University of South Florida. Prior to that, he was a Senior Research and Development Engineer in Advanced Design, Intel Corp. At Intel, his research was focused on low power and robust embedded memory design in scaled technologies. His research interests include low-power circuits, hardware security, quantum computing and digital testing for nanometer technologies.

Dr. Ghosh served as Associate Editor of the IEEE Transactions On Computer-Aided Design (2019-) and IEEE Transactions On Circuits and Systems I (2014-2015) and as Senior Editorial Board member of IEEE Journal of Emerging Topics on Circuits and Systems (JETCAS) (2016-2018). He served as Guest Editor of the IEEE JETCAS (2015-2016) and IEEE Transactions On VLSI Systems (2018-2019). He has also served in the technical program committees of ACM/IEEE conferences such as, DAC, ICCAD, CICC, DATE, ISLPED, GLSVLSI, Nanoarch and ISQED. He served as Program Chair of ISQED (2019) and DAC Ph.D. Forum (2016) and track (co)-Chair of CICC (2017-2019), ISLPED (2017-2018) and ISQED (2016-2017).

Dr. Ghosh is a recipient of Intel Technology and Manufacturing Group Excellence Award in 2009, Intel Divisional Award in 2011, Intel Departmental Awards in 2011 and 2012, USF Outstanding Research Achievement Award in 2015, College of Engineering Outstanding Research Achievement Award in 2015, DARPA Young Faculty Award (YFA) in 2015, ACM SIGDA Outstanding New Faculty Award in 2016, YFA Director’s Fellowship in 2017, Monkowsky Career Development Award in 2018, Lutron Spira Teaching Excellence Award in 2018 and Dean's Certificate of Excellence in 2019. He is a Senior Member of the IEEE and the National Academy of Inventors (NAI), and, Associate member of Sigma Xi.

Affiliation(s)

Pennsylvania State University

United States

Yier Jin

University of Florida

United States

3 (Southeastern U.S.)

Yier Jin

3 (Southeastern U.S.)

Biography

Yier Jin is the Endowed IoT Term Professor in the Warren B. Nelms Institute for the Connected World and also an Associate Professor in the Department of Electrical and Computer Engineering (ECE) in the University of Florida (UF). Prior to joining UF, he was an assistant professor in the ECE Department at the University of Central Florida (UCF). He received his PhD degree in Electrical Engineering in 2012 from Yale University after he got the B.S. and M.S. degrees in Electrical Engineering from Zhejiang University, China, in 2005 and 2007, respectively. His research focuses on the areas of embedded systems design and security, trusted hardware intellectual property (IP) cores and hardware-software co-design for modern computing systems. He is currently focusing on the design and security analysis on Internet of Things (IoT) and wearable devices with particular emphasis on information integrity and privacy protection in the IoT era. Dr. Jin received Young Investigator Grant from Southeastern Center for Electrical Engineering Education (SCEEE) in 2015, early CAREER award from Department of Energy (DoE) in 2016, Outstanding New Faculty Award (ONFA) from ACM’s Special Interest Group on Design Automation (SIGDA) in 2017, and Young Investigator Award (YIP) from Office of Naval Research (ONR) in 2019. He also received the Best Paper Award of the 52nd Design Automation Conference in 2015, the 21st Asia and South Pacific Design Automation Conference (DAC) in 2016, the 10thIEEE Symposium on Hardware-Oriented Security and Trust (HOST) in 2017, the 2018 ACM Transactions on Design Automation of Electronic Systems (TODAES), the 28thedition of the ACM Great Lakes Symposium on VLSI (GLSVLSI) in 2018, and the Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2019. He is the IEEE Council on Electronic Design Automation (CEDA) Distinguished Lecturer.

Affiliation(s)

University of Florida

United States

Yiorgos Makris

University of Texas, Dallas

United States

5 (Southwestern U.S.)

Embedded Software

Preeti Ranjan Panda

Indian Institute of Technology, Delhi

India

10 (Asia and Pacific)

Preeti Ranjan Panda

10 (Asia and Pacific)

Biography

Preeti Ranjan Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine. He is currently a Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore, and the Advanced Technology Group at Synopsys Inc., Mountain View, and has been a visiting scholar at Stanford University.

His research interests are Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, Hardware/Software Codesign, and Low Power Design. He is the author of two books: Memory issues in Embedded Systems-on-chip: Optimizations and Exploration (Kluwer Academic Publishers) and Power-efficient System Design (Springer). He is a recipient of an IBM Faculty Award , the IESA Techno Mentor Award, and a Department of Science and Technology Young Scientist Award. Research works authored by Prof. Panda and his students have received several honours, including Best Paper nominations at CODES+ISSS, DATE, ASPDAC, and VLSI Design Conference, and Most downloaded paper of ACM TODAES journal.

Prof. Panda currently serves as the Editor-in-Chief of IEEE Embedded Systems Letters (ESL). He has served on the editorial boards of IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) , ACM Transactions on Design Automation of Electronic Systems (TODAES) , IEEE Embedded Systems Letters (ESL), IEEE Transactions on Multi-Scale Computing Systems (TMSCS) and International Journal of Parallel Programming (IJPP), General co-Chair of VLSI Design, and as Technical Program co-Chair of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) and International Conference on VLSI Design and Embedded Systems (VLSI Design). He has also served on the technical program committees and chaired sessions at several conferences in the areas of Embedded Systems and Design Automation, including DAC, ICCAD, DATE, CODES+ISSS, IPDPS, ASPDAC, and EMSOFT.

Affiliation(s)

Indian Institute of Technology, Delhi

India

Embedded Systems

Madhu Mutyam

Indian Institute of Technology, Madras

India

10 (Asia and Pacific)

Zili Shao

The Chinese University of Hong Kong

Hong Kong SAR China

10 (Asia and Pacific)

Jiang Xu

Hong Kong University of Science & Technology

Hong Kong SAR China

10 (Asia and Pacific)

Jiang Xu

10 (Asia and Pacific)

Biography

Jiang Xu (S’02–M’07) received the Ph.D. degree from Princeton University, Princeton, NJ, USA, in 2007.,From 2001 to 2002, he was with Bell Labs, Murray Hill, NJ, USA, as a Research Associate. He was a Research Associate with NEC Laboratories America, Princeton, NJ, USA, from 2003 to 2005. He was with Sandbridge Technologies, Tarrytown, NY, USA, a startup company, from 2005 to 2007, where he developed and implemented two generations of NoC-based ultralow-power multiprocessor systems-on-chip for mobile platforms. He is an Associate Professor with the Hong Kong University of Science and Technology, Hong Kong, where he is the Founding Director of the Xilinx-HKUST Joint Lab and established the Big Data System Lab and Optical/Photonic Technology for Interconnected Computing System Lab. He has authored and co-authored over 100 book chapters and papers in peer-reviewed journals and international conferences. His current research interests include big data system, heterogeneous computing, optical interconnection network, power delivery and management, MPSoC, low-power embedded system, and hardware/software codesign.,Dr. Xu currently serves as the Associate Editor for the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and an Area Editor of Hardware and Architecture Design for ACM Transactions on Embedded Computing Systems. He was an IEEE Distinguished Lecturer and an ACM Distinguished Speaker. He served on the steering committees, organizing committees, and technical program committees of many international conferences.

Affiliation(s)

Hong Kong University of Science & Technology

Hong Kong SAR China

Chengmo Yang

University of Delaware

United States

2 (Eastern U.S.)

Chia-Lin Yang

National Taiwan University

Taiwan

10 (Asia and Pacific)

Emerging Technologies

Abdoulaye Gamatié

University of Montpellier

France

8 (Africa, Europe, Middle East)

Xiaobo Sharon Hu

University of Notre Dame

United States

4 (Central U.S.)

FPGA

William Hung

Cadence Design Systems

United States

5 (Southwestern U.S.)

Wei Zhang

Hong Kong University of Science & Technology

Hong Kong SAR China

10 (Asia and Pacific)

High-level Synthesis

Philippe Coussy

Université de Bretagne-Sud

France

8 (Africa, Europe, Middle East)

Philippe Coussy

8 (Africa, Europe, Middle East)

Biography

Philippe Coussy is a full professor in the Lab-STICC (CNRS) at the Université de Bretagne-Sud, France, where he leads the “Design of Advanced Architectures” group. He was graduated from Université Pierre et Marie Curie (MSc, 1999), Université de Bretagne-Sud (Ph.D., 2003 and Habilitation 2011). He holds the scientific excellence fellowship (PEDR/PES A) since 2008. He is member of the Advisory Board of the GDR on SoC-SIP and chair of the topic “embedded software and hardware architecture” since 2011. He is member of the Advisory Board of the GDR on BioComp and chair of the topic “system design” since 2015. He is a member of the technical committee of the IEEE Signal Processing Society, Design and Implementation of Signal Processing Systems (DISPS) since 2011. He is member of the European Network of Excellence HiPEAC. His research interests include system-level design and methodologies, high-level synthesis, computer-aided design for SoCs, embedded systems, low-power design for FPGAs and neuromorphic computing. He has supervised 16 PhD theses (5 in progress), 16 M.Sc. theses and published more than 60 papers in edited books, journals or conference proceedings on these topics. He holds 5 patents in hardware design domain. He has organized several workshops and tutorials in many outstanding international conferences including DAC, DATE, CODES+ISSS and ASP-DAC. He was guest editor for a special issue of Journal of Electrical and Computer Engineering on “ESL Design Methodology” (2012), guest editor for a special issue of IEEE Design and Test of Computer on “High-Level Synthesis” (2009) and co-editor of the books “High-Level Synthesis: From Algorithm to Digital Circuit” (Springer) (2008) and “Advanced Hardware Design for Error Correcting Codes” (Springer) (2014). He has been a member of the 2009 Catrene EDA roadmap and the 2011 HiPEAC roadmap committees. He regularly serves as a national expert (ANR, MESR) and international expert (Canada, Israel, Portugal…) participates as PC member in many international ACM/IEEE conferences (DATE, ICASSP, ISCAS, ASAP, GLSVLSI, SIPS, DAC, FPL…) and as reviewer for major journals (IEEE TCAD, TECS, JETCAS, D&T of Computers, ACM TODAES, TECS…). He is Associate Editor of the IEEE Signal Processing Letters for the Design and Implementation of signal processing systems (HWD-ARCH), Programmable Hardware e.g. FPGA, SoC or ASIC for DSP Algorithms (HDW-PROG) and Multicore Processors for DSP Algorithms (HDW-MCORE).

Affiliation(s)

Université de Bretagne-Sud

France

Zhiru Zhang

Cornell University

United States

Human Factors in Design

Aviral Shrivastava

Arizona State University

United States

6 (Western U.S.)

Aviral Shrivastava

6 (Western U.S.)

Biography

Aviral Shrivastava is an associate professor in the School of Computing, Informatics, and Decision Systems Engineering at the Arizona State University, where he has established and heads the Compiler and Microarchitecture Labs (CML).

He received his master's degree and doctorate in information and computer science from University of California, Irvine, and bachelor's degree in computer science and engineering from Indian Institute of Technology, Delhi. He is a 2011 National Science Foundation (NSF) CAREER Award recipient, and recipient of 2012 Outstanding Junior Researcher in CSE at ASU. He was also a visiting faculty member in the EECS Department at University of California, Berkeley for 2012-2014.

His research lies at the intersection of compilers and architectures of embedded and multi-core systems, with the goal of improving power, performance, temperature, energy, reliability and robustness. His research is funded by NSF and several industries including Microsoft, Raytheon Missile Systems, Intel Nvidia, and others. He serves on organizing and program committees of several premier embedded system conferences, including ISLPED, CODES ISSS, CASES and LCTES, and regularly serves on NSF and Department of Energy (DOE) review panels.

Education

Ph.D. Computer Science and Engineering, University of California-Irvine 2006
M.S. Computer Science and Engineering, University of California-Irvine 2002
Bachelor’s degree. Computer Science and Engineering, Indian Institute of Technology, Delhi 1999

Affiliation(s)

Arizona State University

United States

Machine Learning/AI Automation

Peter A. Beerel

University of Southern California

United States

6 (Western U.S.)

Peter A. Beerel

6 (Western U.S.)

Biography

Peter Beerel received his B.S.E. degree in Electrical Engineering from Princeton University in 1989, and his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1991 and 1994, respectively. He joined the Department of Electrical Engineering-Systems at the University of Southern California's Viterbi School of Engineering in 1994, where he is currently a Full Professor. Dr. Beerel was the Faculty Director of Innovation Studies at the USC Stevens Institute for Innovation from 2006 to 2008. In May of 2008, he took a leave of absence from USC and co-founded TimeLess Design Automation with one of his Ph.D. students, Dr. Georgios Dimou. Their mission was to demonstrate and commercialize an asynchronous ASIC flow for high-performance systems. They were successful and sold the company in July of 2010 to Fulcrum Microsystems which was acquired by Intel in 2011. In 2015, his Ph.D. student, Dylan Hand, co-founded a second company, Reduced Energy Microsystems, to commercialize an asynchronous ASIC flow for ultra-low-power vision and machine learning systems. Dr. Beerel joined REM as Chief Scientist in 2016.

Dr. Beerel's research interests include a variety of topics in CAD and asynchronous VLSI design. He has been a member of the technical program committee for the International Symposium on Advanced Research in Asynchronous Circuits and Systems since 1997, was program co-chair for ASYNC'98, and was general co-chair for ASYNC'07. Dr. Beerel was recipient of a VSoE Outstanding Teaching Award in 1997 and the VSoE Junior Research Award in 1998. He received a National Science Foundation CAREER Award and a 1995 Zumberge Fellowship. He was also co-winner of the Charles E. Molnar award for two papers published in ASYNC'97 that best bridged theory and practice of asynchronous system design, was co-recipient of the best paper award in ASYNC'99, and winner of the best paper award in ASYNC'2014. He was the 2008 recipient of the IEEE Region 6 Outstanding Engineer Award for significantly advancing the application of asynchronous circuits to modern VLSI chips.

Affiliation(s)

University of Southern California

United States

Claudionor N. Coelho, Jr.

Google LLC

United States

6 (Western U.S.)

Sicun Gao

University of California, San Diego

United States

6 (Western U.S.)

Frank Liu

Oak Ridge National Laboratory

United States

3 (Southeastern U.S.)

Diana Marculescu

University of Texas, Austin

United States

5 (Southwestern U.S.)

Li-C Wang

University of California, Santa Barbara

United States

6 (Western U.S.)

Modeling & Simulation

Chung-Kuan Cheng

University of California, San Diego

United States

6 (Western U.S.)

Eric Keiter

Sandia National Laboratories

United States

6 (Western U.S.)

Ngai Wong

The University of Hong Kong

Hong Kong SAR China

10 (Asia and Pacific)

Wenjian Yu

Tsinghua University

China

10 (Asia and Pacific)

Physical Design

Laleh Behjat

University of Calgary

Canada

7 (Canada)

Stephan Held

University of Bonn

Germany

8 (Africa, Europe, Middle East)

Iris Hui-Ru Jiang

National Taiwan University

Taiwan

10 (Asia and Pacific)

Iris Hui-Ru Jiang

10 (Asia and Pacific)

Biography

Iris Hui-Ru Jiang received the B.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan. She has been with National Chiao Tung University, Hsinchu, Taiwan, from 2005 to 2017. She is currently a Professor with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan. She has been a Visiting Scholar with IBM Austin Research Laboratory, Austin, TX, USA, from 2013 to 2014. Her current research interests include physical design optimization, interaction between logic design and physical synthesis, timing analysis and optimization, design for manufacturability, and data analytics-based design automation.

Dr. Jiang was a recipient of the Best Paper Award Nomination from Design Automation Conference (DAC) 2016 and International Symposium on Physical Design (ISPD) 2013, the Best in-track Paper Award from International Conference on Computed Aided Design (ICCAD) 2014, the 2011 Outstanding Young Electrical Engineer Award and 2018 Outstanding Electrical Engineering Professor Award from Chinese Institute of Electrical Engineering. She and her students were the recipients of the First Place Award at the CAD Contest at ICCAD in 2012, two Third Place Awards at the TAU Timing Analysis Contests in 2013 and 2014, four First Place Awards at the TAU Timing Analysis Contest in 2015, 2017, 2018, and 2019.

She is currently the Chair of IEEE CEDA Design Automation Technical Committee and has organized CAD contest at ICCAD from 2012 to 2014 and [email protected], since 2016. She is currently an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and has served on technical program committees of major EDA conferences, including DAC, ICCAD, ISPD, etc. She is a member of the Phi Tau Phi Scholastic Honor Society.

Affiliation(s)

National Taiwan University

Taiwan

David Pan

University of Texas at Austin

United States

5 (Southwestern U.S.)

Safety, Resilience, Security

Abhijit Chatterjee

Georgia Institute of Technology

United States

3 (Southeastern U.S.)

Abhijit Chatterjee

3 (Southeastern U.S.)

Biography

Abhijit Chatterjee is a professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA’s New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC).

Dr. Chatterjee has authored over 425 papers in refereed journals and meetings and has 23 patents. He has supervised 43 doctoral dissertations in broad areas of Computer Engineering at Georgia Tech. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems. He served as the chair of the VLSI Technical Interest Group at Georgia Tech from 2010-2012.

Affiliation(s)

Georgia Institute of Technology

United States

Secure, Reliable Systems

Maciej Ciesielski

University of Massachusetts Amherst

United States

1 (Northeastern U.S.)

Jörg Henkel

Karlsruhe Institute of Technology (KIT)

Germany

8 (Africa, Europe, Middle East)

Jörg Henkel

8 (Africa, Europe, Middle East)

Biography

Prof. Jörg Henkel is with Karlsruhe Institute of Technology (KIT), Germany, where he is directing the Chair for Embedded Systems CES. Before, he was a Senior Research Staff Member at NEC Laboratories in Princeton, NJ. He received his PhD from Braunschweig University with "Summa cum Laude".

Prof. Henkel has/is organizing various embedded systems and low power ACM/IEEE conferences/symposia as General Chair and Program Chair and was a Guest Editor on these topics in various journals like the IEEE Computer Magazine.

He was Program Chair of CODES'01, RSP'02, ISLPED’06, SIPS'08, CASES'09, Estimedia'11, VLSI Design'12, ICCAD’12, PATMOS’13, NOCS’14 and served as General Chair for CODES'02, ISLPED’09, Estimedia’12, ICCAD’13 and ESWeek'16. He is/has been a steering committee member of major conferences in the embedded systems field like at ICCAD, ESWeek, ISLPED, Codes+ISSS, CASES and is/has been an editorial board member of various journals like the IEEE TVLSI, IEEE TCAD, IEEE TMSCS, ACM TCPS, JOLPE, etc.

In recent years, Prof. Henkel has given more than ten keynotes at various international conferences primarily with focus on embedded systems dependability. He has given full/half-day tutorials at leading conferences like DAC, ICCAD, DATE, etc. Prof. Henkel received the 2008 DATE Best Paper Award, the 2009 IEEE/ACM William J. Mc Calla ICCAD Best Paper Award, the Codes+ISSS 2015, 2014, and 2011 Best Paper Awards, and the MaXentric Technologies AHS 2011 Best Paper Award as well as the DATE 2013 Best IP Award and the DAC 2014 Designer Track Best Poster Award. He is the Chairman of the IEEE Computer Society, Germany Section, and was the Editor-in-Chief of the ACM Transactions on Embedded Computing Systems (ACM TECS) for two consecutive terms.
He is an initiator and the coordinator of the German Research Foundation's (DFG) program on 'Dependable Embedded Systems' (SPP 1500). He is the site coordinator (Karlsruhe site) of the Three-University Collaborative Research Center on "Invasive Computing" (DFG TR89). He is the Editor-in-Chief of the IEEE Design&Test Magazine. He holds ten US patents and is a Fellow of the IEEE.

Affiliation(s)

Karlsruhe Institute of Technology (KIT)

Germany

Subhasish Mitra

Stanford University

United States

6 (Western U.S.)

Subhasish Mitra

6 (Western U.S.)

Biography

Subhasish Mitra is currently a Professor of Electrical Engineering and Computer Science at Stanford University, Stanford, CA, USA, where he directs the Stanford Robust Systems Group and co-leads the computation focus area of the Stanford SystemX Alliance. He is also a Faculty Member with the Neurosciences Institute, Stanford University. He holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI, Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation, Santa Clara, CA, USA. His current research interests include broadly across robust computing, nanosystems, VLSI design, validation, test, and electronic design automation, and neurosciences. He along with his students and collaborators demonstrated the first carbon nanotube computer and the first 3-D nanosystem with computation immersed in data storage. These demonstrations received widespread recognitions (cover of Nature, Research Highlight to the U.S. Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, The Economist, Electronic Engineering Times, IEEE Spectrum, MIT Technology Review, National Public Radio, The New York Times, Scientific American, Time, The Wall Street Journal, The Washington Post, and numerous others worldwide). His earlier work on X-Compact test compression has been a key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial electronic design automation tools. He is a Fellow of the Association for Computing Machinery (ACM) and IEEE. He received the Association for Computing Machinery Special Interest Group on Design Automation/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test-of-time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel's highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He along with his students published several award-winning papers at major venues, including the ACM/IEEE Design Automation Conference, the IEEE International Solid-State Circuits Conference, the ACM/IEEE International Conference on Computer-Aided Design, the IEEE International Test Conference, the IEEE Transactions on Computer-Aided Design, the IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. He was honored several times by graduating seniors for being important to them during their time at Stanford. He has served on the Defense Advanced Research Projects Agency's Information Science and Technology Board as an Invited Member.

Affiliation(s)

Stanford University

United States

Sudeep Pasricha

Colorado State University

United States

5 (Southwestern U.S.)

Sudeep Pasricha

5 (Southwestern U.S.)

Biography

Sudeep Pasricha is a Monfort Professor and Rockwell-Anderson Professor in the Department of Electrical and Computer Engineering and the Department of Computer Science at Colorado State University, where he is also the Chair of Computer Engineering and Director of the Embedded Systems and High-Performance Computing (EPiC) Laboratory. His research interests are broadly in the areas of energy-efficient, fault-resilient, and secure computing, for platforms encompassing embedded systems (cyber-physical systems), mobile computing (internet-of-things), and high-performance computing (datacenters, supercomputers). More specific topics of interest include: 1) on-chip and chip-to-chip network design, 2) memory architecture design, 3) design with emerging technologies, e.g., silicon photonics, 4) middleware and embedded software design, 5) algorithms for multi-objective optimization, 6) real-time system design, and 7) VLSI design, and 8) resource allocation/scheduling techniques. He also works on applications of technology to automotive systems (he is the ECE faculty lead for the controls and ADAS design activities on the Ecocar3 project, and also involved with powertrain control software development for a leading automotive company), robotics, therapy, mobile sensing, smart infrastructure, and workflow automation. Details of ongoing and past research projects can be found here.

Prof. Pasricha received the B.E. degree in electronics and communication engineering from Delhi Institute of Technology, Delhi, India, in 2000, and his M.S. and Ph.D. degrees in computer science from the University of California, Irvine in 2005 and 2008. He joined Colorado State University (CSU) in 2008. Prior to joining CSU, he spent several years working in semiconductor companies including STMicroelectronics and Conexant. He has written a book, contributed several book chapters, and published over 160 research articles in peer-reviewed conferences and journals that have received more than 2600 citations. He holds a patent and has presented several tutorials at premier conferences. He has graduated 6 Ph.D. and 8 M.S students.

His research has been recognized with five Best Paper Awards at the ACM SLIP 2016, ACM GLSVLSI 2015, IEEE AICCSA 2011, IEEE ISQED 2010 and ACM/IEEE ASPDAC 2006 conferences, as well as three Best Paper Award Finalist selections at IEEE ISQED 2016, IEEE SCNS 2016, and ACM/IEEE DAC 2005. He has received several fellowships and awards for excellence in research and teaching, including the 2016-2019 Walter Scott Jr. College of Engineering Rockwell-Anderson Professorship, the 2016-2018 University Distinguished Monfort Professorship, the 2015 IEEE/TCSC Award for Excellence for a mid-career researcher, and the 2014 George T. Abell Outstanding mid-career faculty award. His research is sponsored by research grants from the National Science Foundation (NSF), Semiconductor Research Corporation (SRC), Fiat-Chrysler Corporation, Air Force Office of Scientific Research (AFOSR), Oak Ridge National Lab (ORNL), and National Aeronautics and Space Administration (NASA), including the AFOSR Young Investigator Award in 2013, as well as grants from Intel, HP, AMD, Microsoft, Xilinx, Altera, ARM, and RIM/Blackberry.

Affiliation(s)

Colorado State University

United States

Qiang Xu

Chinese University of Hong Kong

Hong Kong SAR China

10 (Asia and Pacific)

Hao Zheng

University of South Florida

United States

3 (Southeastern U.S.)

Synthesis and Verification

Jordi Cortadella

Universitat Politècnica de Catalunya

Spain

Rolf Drechsler

University of Bremen

Germany

8 (Africa, Europe, Middle East)

Rolf Drechsler

8 (Africa, Europe, Middle East)

Biography

Rolf Drechsler received the Diploma and Dr. phil. nat. degrees in computer science from the Johann Wolfgang Goethe University in Frankfurt am Main, Frankfurt am Main, Germany, in 1992 and 1995, respectively. He worked at the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and at the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001.

Since October 2001, Rolf Drechsler is Full Professor and Head of the Group of Computer Architecture, Institute of Computer Science, at the University of Bremen, Germany. In 2011, he additionally became the Director of the Cyber-Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI) in Bremen.
His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. He is an IEEE Fellow.

From 2008 to 2013 he was the Vice Rector for Research and Young Academics at the University of Bremen. Since 2018 he is the Dean of the Faculty of Mathematics and Computer Science.

Rolf Drechsler was a member of Program Committees of numerous conferences including e.g., DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, and FMCAD. He was Symposiums Chair at ISMVL 1999 and 2014, and the Topic Chair for "Formal Verification" at DATE 2004, DATE 2005, DAC 2010, and DAC 2011 and 2018. He received the Berninghausen Award for Excellence in Teaching in 2018.
He is a co-founder of the Graduate School of Embedded Systems and he is the coordinator of the Graduate School "System Design" funded within the German Excellence Initiative.
He received best paper awards at the Haifa Verification Conference (HVC) in 2006, the Forum on specification & Design Languages (FDL) in 2007 and 2010, the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) in 2010 and the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2013 and 2018.

Rolf Drechsler is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration Systems, IET Cyber-Physical Systems: Theory & Applications, International Journal on Multiple-Valued Logic and Soft Computing, and ACM Journal on Emerging Technologies in Computing Systems.

Affiliation(s)

University of Bremen

Germany

Phillip Stanley-Marbell

University of Cambridge

United Kingdom

8 (Africa, Europe, Middle East)

System-Level Design

Luca Carloni

Columbia University

United States

1 (Northeastern U.S.)

Ayse Coskun

Boston University

United States

1 (Northeastern U.S.)

Hai (Helen) Li

Duke University

United States

3 (Southeastern U.S.)

Yu Wang

Tsinghua University

China

1 (Northeastern U.S.)

Test

Anne Gattiker

IBM Research, Austin

United States

5 (Southwestern U.S.)

Xiaowei Li

Chinese Academy of Sciences (CAS)

China

10 (Asia and Pacific)

Xiaowei Li

10 (Asia and Pacific)

Biography

Xiaowei Li (SM'04) received the BEng and MEng degrees in computer science from the Hefei University of Technology, Hefei, China, in 1985 and 1988, respectively, and the PhD degree in computer science from the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), Beijing, China, in 1991. He was an associate professor with the Department of Computer Science and Technology, Peking University, Beijing, from 1991 to 2000. In 2000, he joined ICT, CAS, as a professor, where he is currently the deputy director of the State Key Laboratory of Computer Architecture. He has co-authored more than 280 papers in journals and international conferences, and he holds 60 patents and 30 software copyrights. His current research interests include VLSI testing, design for testability, design verification, dependable computing, and wireless sensor networks. He has been the vice-chair of the IEEE Asia & Pacific Regional Test Technology Technical Council (TTTC) since 2004. He is currently vice-chair of IEEE TTTC. He was the chair of the Technical Committee on Fault Tolerant Computing, China Computer Federation (2008-2012), and Steering Committee chair of IEEE Asian Test Symposium (2011-2013). He was Steering Committee Chair of IEEE Workshop on RTL and High Level Testing (2007-2010). He services as associate editor of the Journal of Computer Science and Technology, the Journal of Low Power Electronics, JETTA and TCAD. He is a senior member of the IEEE.

Affiliation(s)

Chinese Academy of Sciences (CAS)

China

Nicola Nicolici

McMaster University

Canada

7 (Canada)

Alex Orailoglu

University of California, San Diego

United States

6 (Western U.S.)

TCAD Editor-at-Large Board

Sharad Malik

Princeton University

United States

1 (Northeastern U.S.)

Sharad Malik

1 (Northeastern U.S.)

Biography

Sharad Malik (F’02) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India, in 1985, and the M.S. and Ph.D. degrees in computer science from the University of California at Berkeley, Berkeley, CA, USA, in 1987 and 1990, respectively.

He served as the Director of the Keller Center for Innovation in Engineering Education, Princeton University, Princeton, NJ, USA, from 2006 to 2011. He is the George Van Ness Lothrop Professor of Engineering with Princeton University and the Chair of the Department of Electrical Engineering. He has served as the Director of the multi-university MARCO Gigascale Systems Research Center, Berkeley, CA, USA, from 2009 to 2012, and as the Associate Director of the Center for Future Architectures Research, Ann Arbor, MI, USA, from 2013 to 2016. His research in functional timing analysis and propositional satisfiability has been widely used in industrial electronic design automation tools. His current research interest includes design methodology and design automation for computing systems.

Dr. Malik has received the IEEE/ACM Design Automation Conference Award for the most cited paper in the 50-year history of the conference in 2013, the Computer-Aided Verification Award for fundamental contributions to the development of high-performance Boolean satisfiability solvers in 2009, the IEEE/ACM International Conference on Computer-Aided Design Ten Year Retrospective Most Influential Paper Award in 2011, the IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation in 2017, the Princeton University Presidents Award for Distinguished Teaching in 2009, the IIT Delhi Distinguished Alumni Award in 2009, as well as several other research and teaching awards. He is a fellow of the ACM.

Affiliation(s)

Princeton University

United States

Rob A. Rutenbar

University of Pittsburgh

United States

2 (Eastern U.S.)

Rob A. Rutenbar

2 (Eastern U.S.)

Biography

Rob A. Rutenbar is the Senior Vice Chancellor for Research, and provides strategic vision, leadership, and partnership expertise that helps University of Pittsburgh researchers and scholars advance their world-class research, scholarship, and innovation. He is responsible for advancing Pitt’s mission to expand the frontiers of knowledge and positively impact the world through collaborative and multidisciplinary approaches to research.

He leads five offices focused on the full breadth of the research enterprise -- from pursuing and securing sponsorships and funding, through ensuring adherence to the highest standards to research conduct, and providing cutting-edge resources to researchers, to creative collaborations that lead to successful commercialization.

Dr. Rutenbar possesses nearly 40 years of experience in innovation and technology. His research focuses on three broad categories: tools for a wide variety of integrated circuit design issues, methods for managing the statistics of nanoscale chip design, and custom computer architectures for perceptual and data analytics problems.

Prior to coming to the University of Pittsburgh, he served as the Abel Bliss Professor of Engineering and head of the Department of Computer Science at the University of Illinois at Urbana-Champaign, where he oversaw a department composed of 70 faculty members and nearly 2,500 students consistently ranked as the No. 5 Computer Science program in the nation by U.S. News and World Report. Prior to assuming that position in 2010, Dr. Rutenbar held the Stephen J. Jatras Chair in Electrical and Computer Engineering at Carnegie Mellon University, where he served on the engineering faculty for 25 years.

As an entrepreneur, Dr. Rutenbar founded the tech firms Neolinear Inc. and Voci Technologies, Inc. in 1998 and 2006, respectively. He was the founding director for the Center for Circuit and System Solutions, a multi-university consortium that focused on next-generation chip design challenges. The recipient of 14 U.S. patent grants, his endeavors have been funded by such notable entities as AT&T, Google, DARPA, IBM, the National Science Foundation and the Pennsylvania Infrastructure Technology Alliance. Dr. Rutenbar is the author of eight books and 175 published research articles.

In recognition of his career accomplishments, Dr. Rutenbar was elected a fellow of both the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE). He is a winner of the Semiconductor Research Corporation’s Aristotle Award, given in recognition of the impact of his students on the U.S. semiconductor industry, and the IEEE CEDA/ESDA Phil Kaufman Award, for his lifetime contributions to tools for chip design. He was also recognized with distinguished alumnus awards from both the University of Michigan and Wayne State University. Dr. Rutenbar is also among the top scientists to be elected both as an American Association for the Advancement of Science Fellow and as a National Academy of Inventors (NAI) Fellow. Election to NAI Fellow is the highest professional distinction for academic inventors.

In addition to his research career, Dr. Rutenbar is also a committed educator. He led efforts at Illinois to explore massive, open online courses (MOOCs) and launched the first MOOC on chip design tools. His course is currently the largest such educational offering available globally and has had over 60,000 registered learners since its 2013 debut.

Dr. Rutenbar earned his bachelor’s degree in electrical engineering at Wayne State University in 1978. He earned master’s and doctorate degrees in computer information and control engineering at the University of Michigan in 1979 and 1984, respectively.

Affiliation(s)

University of Pittsburgh

United States

Sachin Sapatnekar

University of Minnesota

United States

4 (Central U.S.)

Website

Sachin Sapatnekar

4 (Central U.S.)

Website

Biography

Sachin Sapatnekar received the B. Tech. degree from the Indian Institute of Technology, Bombay in 1987, the M. S. degree from Syracuse University in 1989, and the Ph. D. degree from the University of Illinois at Urbana-Champaign in 1992. He worked at Texas Instruments during the summer of 1990, and at Intel Corporation during the summer of 1997. His other major educational qualifications include self-taught basic juggling under the long-distance tutelage of the world-renowned Klutz School in 1991, and the PADI Open Water Diver Certification from Deep Sea Divers Den in 2001. With his once-a-decade average of trying something new, he is sure to remain his same old boring self until 2011. So boring that it's well past 2011, and this hasn't been updated.

He was an Assistant Professor in the Department of Electrical and Computer Engineering at Iowa State University from 1992 to 1997. He is currently a Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, where he holds the Robert and Marjorie Henle chair and the Distinguished McKnight University Professorship. His current research interests lie in developing efficient techniques for computer-aided design of integrated circuits and are primarily centered around physical design, timing and simulation issues, and optimization algorithms. He has served on the editorial boards of several IEEE journals, including as Editor-in-Chief of the IEEE Transactions on CAD. He was a Technical Program Co-chair in 2006 and 2007 for the Design Automation Conference (DAC), and the General Chair in 2010. He has also been the Technical Program Chair and General Chair for the International Symposium on Physical Design (ISPD) and the Tau workshop, and Program Chair for the International Conference on VLSI Design in India. He is a recipient of the NSF Career Award, the SRC Technical Excellence Award, the SIA University Researcher Award, Best Paper Awards at the DAC'97, ICCD'98, DAC'01 DAC'03, ISPD'09, ISQED'10, and ASYNC'16 conferences, a Best Poster Award at IRPS'12, and the ICCAD Ten-Year Retrospective Most Influential Paper Award in 2013 and 2016. He has been a Fulbright Senior Researcher at Universitat Politècnica de Catalunya in Barcelona in 2013, and a DJ Gandhi Visiting Professor at the Indian Institute of Technology, Bombay in 2014. He is a Fellow of the IEEE (2003) and the ACM (2016).

Affiliation(s)

University of Minnesota

United States

Alberto Sangiovanni-Vincentelli

University of California, Berkeley

United States

6 (Western U.S.)

Alberto Sangiovanni-Vincentelli

6 (Western U.S.)

Biography

Alberto Sangiovanni Vincentelli is the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Sciences at the University of California at Berkeley. In 1980-1981, he was a Visiting Scientist at the Mathematical Sciences Department of the IBM T.J. Watson Research Center. In 1987, he was Visiting Professor at MIT. He is an author of over 800 papers, 17 books and 2 patents in the area of design tools and methodologies, large scale systems, embedded systems, hybrid systems and innovation. He was a co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation and the founder and Scientific Director of the PARADES Research Center in Rome.

Board Participation: • Public Companies: He has been a member of the Board of Directors of Cadence and of KPIT-Cummins. • Privately Held Companies: He is a member of the Board of Directors of Sonics, and of Expert Systems. • Advisory Boards: He had been a member of the ST microelectronics Advisory Board for 10 years. He was a member of the HP Strategic Technology Advisory Board (2005-2007), a member of the Science and Technology Advisory Board of General Motors (2003-2013), and is a member of the Technology Advisory Council of United Technologies Corporation (2005-present). He is a member of the Advisory Board of Innogest, Xseed and a member of the Investment Committee of Atlante Ventures and Fondo Next. Since January 2013, he is the President of the Strategic Committee of the Italian Strategic Fund. He is member of the Scientific Council of the Italian National Science Foundation (CNR). Since February 2010, he has been a member of the Executive Committee of the Italian Institute of Technology. Since July 2012, he has been named Chairperson of the Comitato Nazionale Garanti per la Ricerca.

Affiliation(s)

University of California, Berkeley

United States

Yervant Zorian

Synopsys, Inc.

United States

10 (Asia and Pacific)

Yervant Zorian

10 (Asia and Pacific)

Biography

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.

He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Affiliation(s)

Synopsys, Inc.

United States