To recognize the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Historical Background: The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award is sponsored by the IEEE Council on EDA and recognizes the best paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems publication. The award is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research. Anyone who is an author of a paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award is eligible for nomination. Prize: $500 for each author (maximum of $2,000 per award) and Certificate plaque Funding: Funded by the IEEE Council on Electronic Design Automation. Presentation: Presented annually at DAC. Basis for Judgement: General quality, originality, contributions, subject matter, and timeliness. Eligibility: Authors of papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award. Nomination Details: Nomination deadline is 28 February of the award year. Nominate for this Award Award Recipients 2018 Luca G. Amaru, Pierre-Emmanuel Gaillardon, Giovanni De Micheli 2018 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Giovanni De Micheli, Luca Amaru, and Pierre-Emmanuel Gaillardon Paper(s) × Majority-Inverter Graph: A New Paradigm for Logic Optimization IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Vol. 35, Issue 5, pp. 806 - 819, May 2016 https://ieeexplore.ieee.org/document/7293649 07293649.pdf 2017 Xiaoqing Jin, Alexandre Donzé, Jyotirmoy V. Deshmukh, Sanjit A. Seshia 2017 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Mining Requirements from Closed-Loop Control Models “Mining Requirements from Closed-Loop Control Models,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 11, pp. 1704 – 1717, November 2015. http://ieeexplore.ieee.org/document/7084172/ 2016 Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, Ben Gu 2016 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 7, pp. 1096 - 1109, July 2015. http://ieeexplore.ieee.org/document/7046346/ 2015 Kai Hu, Feiqiao Yu, Tsung-Yi Ho, Krishnendu Chakrabarty 2015 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, Issue 10, pp. 1463 - 1475, October 2014 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6899781 2014 Zheng Zhang, Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel 2014 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol. 32, Issue: 10, pp. 1533 - 1545, September 2013. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6600994 2013 Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob Rutenbar, Ronald D. (Shawn) Blanton - Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award, Ronald D. (Shawn) Blanton 2013 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol. 30, Issue: 12, pp. 1814 - 1827, December 2011. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6071091&isnumber=6071079&tp= 2012 Umit Ogras, Paul Bogdan, Radu Marculescu 2012 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × An Analytical Approach for Network-on-Chip Performance Analysis IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol, 29, No. 12, pp. 2001-2013, December 2010. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=908471&isnumber=19612&tp= 2011 Amith Singhee, Amith Singhee, Rob Rutenbar - Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award 2011 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 8, pp. 1176-1189, August 2009. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5166555 2010 Chris Chu, Yiu-Chung Wong 2010 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 70-83, January 2008. http://ieeexplore.ieee.org/iel5/43/4358296/04358497.pdf?arnumber=4358497 2009 Hristo Nikolov, Todor Stefanov, Ed F. Deprettere 2009 Recipient of IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award View paper(s) Paper(s) × Systematic and Automated Multiprocessor System Design, Programming, and Implementation IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 542-555, March 2008. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4378214&tp= Pagination 1 2 › ›› » Last »
Majority-Inverter Graph: A New Paradigm for Logic Optimization IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Vol. 35, Issue 5, pp. 806 - 819, May 2016 https://ieeexplore.ieee.org/document/7293649 07293649.pdf
Mining Requirements from Closed-Loop Control Models “Mining Requirements from Closed-Loop Control Models,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 11, pp. 1704 – 1717, November 2015. http://ieeexplore.ieee.org/document/7084172/
Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 7, pp. 1096 - 1109, July 2015. http://ieeexplore.ieee.org/document/7046346/
Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, Issue 10, pp. 1463 - 1475, October 2014 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6899781
Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol. 32, Issue: 10, pp. 1533 - 1545, September 2013. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6600994
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , Vol. 30, Issue: 12, pp. 1814 - 1827, December 2011. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6071091&isnumber=6071079&tp=
An Analytical Approach for Network-on-Chip Performance Analysis IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol, 29, No. 12, pp. 2001-2013, December 2010. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=908471&isnumber=19612&tp=
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 8, pp. 1176-1189, August 2009. http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5166555
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 1, pp. 70-83, January 2008. http://ieeexplore.ieee.org/iel5/43/4358296/04358497.pdf?arnumber=4358497
Systematic and Automated Multiprocessor System Design, Programming, and Implementation IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 542-555, March 2008. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4378214&tp=
