To recognize the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Historical Background: The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award is sponsored by the IEEE Council on EDA and recognizes the best paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems publication. The award is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research. Anyone who is an author of a paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award is eligible for nomination. Prize: $500 for each author (maximum of $2,000 per award) and certificate Funding: Funded by the IEEE Council on Electronic Design Automation. Presentation: The award will be presented at the ICCAD conference. Basis for Judging: General quality, originality, contributions, subject matter, and timeliness. Eligibility: Authors of papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award. Self Nominations are permitted. Each nominator may only nominate one paper only. Nomination Details: The nomination deadline is 28 February of the award year. Nomination Form: Nominate for this Award Recipients 2023 "DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume: 40; Issue: 11, November 2021 Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, and Shimeng Yu Acceptance Speech × 2022 "Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume: 39, Issue: 6, June 2020 Bon Woong Ku, Kyungwook Chang, and Sung Kyu Lim Acceptance Speech × 2021 "Hardware/Software Co-Exploration of Neural Architectures " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, Issue 12, Dec. 2020 Weiwen Jiang, Lei Yang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Shouzhen Gu, Sakyasingha Dasgupta, Yiyu Shi, and Jingtong Hu Acceptance Speech × "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, Issue 4, April 2021 Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, and David Z. Pan Acceptance Speech × 2020 "An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 7, pp. 1226-1236, July 2019 Alwin Zulehner, Alexandru Paler, and Robert Wille Acceptance Speech × Presentation Photo × 2019 "YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 1, pp. 48-60, Jan. 2018 Renzo Andri, Lukas Cavigelli, Davide Rossi, and Luca Benini Acceptance Speech × Presentation Photo × President Atienza, VP Pubs Silveira, Renzo Andrii, Lukas Cavigelli, VP Awards Mitra 2019 "Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, Issue 11, pp. 2072 - 2085, November 2019 Chen Zhang, Guangyu Sun, Zhenman Fang, Peipei Zhou, Peichen Pan, and Jason Cong Acceptance Speech × Presentation Photo × D. Atienza, L.M. Silveira, P. Zhou, J. Cong, C. Zhang, S. Mitra 2018 "Majority-Inverter Graph: A New Paradigm for Logic Optimization" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, Issue 5, pp. 806 - 819, May 2016 Luca G. Amaru, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli Acceptance Speech × Presentation Photo × Giovanni De Micheli, Luca Amaru, and Pierre-Emmanuel Gaillardon 2017 "Mining Requirements from Closed-Loop Control Models" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 11, pp. 1704 – 1717, November 2015 Xiaoqing Jin, Alexandre Donzé, Jyotirmoy V. Deshmukh, and Sanjit A. Seshia Acceptance Speech × Presentation Photo × Seshia, Donzé, Jin, Deshmukh, and VP Awards H. Onodera 2016 "Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 7, pp. 1096 - 1109, July 2015 Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, and Ben Gu Acceptance Speech × Pagination 1 2 3 ›› Next page Last » Last page
"DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume: 40; Issue: 11, November 2021
"Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume: 39, Issue: 6, June 2020
"Hardware/Software Co-Exploration of Neural Architectures " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, Issue 12, Dec. 2020
"DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, Issue 4, April 2021
"An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 7, pp. 1226-1236, July 2019
"YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 1, pp. 48-60, Jan. 2018
"Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, Issue 11, pp. 2072 - 2085, November 2019
"Majority-Inverter Graph: A New Paradigm for Logic Optimization" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, Issue 5, pp. 806 - 819, May 2016
"Mining Requirements from Closed-Loop Control Models" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 11, pp. 1704 – 1717, November 2015
"Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 7, pp. 1096 - 1109, July 2015