A. Richard Newton Technical Impact Award in Electronic Design Automation

To honor a person or persons for an outstanding technical contribution within the scope of electronic design automation, as evidenced by a paper published at least ten years before the presentation of the award.

Historical Background:

A. Richard Newton, one of the foremost pioneers and leaders of the EDA field, passed away on 2 January 2007, of pancreatic cancer at the age of 55.

A. Richard Newton was professor and dean of the College of Engineering at the University of California, Berkeley. Newton was educated at the University of Melbourne and received his bachelor’s degree in 1973 and his master’s degree in 1975. In the early 1970’s he began to work on SPICE, a simulation program initially developed by Larry Nagel and Donald Pederson to analyze and design complex electronic circuitry with speed and accuracy. In 1978, Newton earned his Ph.D. in electrical engineering and computer sciences from UC Berkeley.

For his research and entrepreneurial contributions to the electronic design automation industry, he was awarded the 2003 Phil Kaufman Award, the highest recognition for contributions to the EDA field. In 2004, he was named a member of the National Academy of Engineering, and in 2006, of the American Academy of Arts and Sciences. He was a member of the Association for Computing Machinery and a fellow of the Institute of Electrical and Electronics Engineers.

Prize:

$1,500 and Plaque for each author. The honoraria will be shared by all authors. For groups of more than five awardees, there will be a minimum of $300 honorarium per contributor.

Funding:

Funded by the IEEE Council on Electronic Design Automation and ACM Special Interest Group on Design Automation.

Presentation:

Presented annually at the Design Automation Conference (DAC).

Basis for Judging:

The impact of the paper which has made an outstanding technical contribution in the scope of electronic design automation through a paper published at least ten years before the award is presented. The award shall be based on the impact of the paper in the field of electronic design automation published ten years or more before the year the award is presented.

Eligibility:

Open to authors of a paper in the field of electronic design automation published ten years or more before the award is presented. The paper must have passed through a peer-review process before publication, be an archived conference or journal publication available from or published by either ACM or IEEE, and be a seminal paper where an original idea was first described. Follow-up papers and extended descriptions of the work may be cited in the nomination, but the award is given for the initial original contribution.

Nomination Details:

The deadline for submitting nominations for the award year is 28 February of that same year.

Nomination Form:

Nominate for this Award

Recipients

2022

"Efficient Steady-State Analysis based on Matrix-Free Krylov-Subspace Methods"

Published in 32nd Design Automation Conference, June 1995

Ricardo Telichevesky, Kenneth S. Kundert

, and Jacob K. White

2021

"Transition Fault Simulation"

Published in IEEE Design&Test, April 1987, Volume 4, Issue 1, pp. 32-38

John A. Waicukauski, Eric Lindbloom, Barry K. Rosen, and Vijay S. Iyengar

2020

"Networks on Chips: A New SoC Paradigm"

Published in IEEE Computer, January 2002, Volume 35, Issue 1, pp. 70-78

Luca Benini

, and Giovanni De Micheli

Giovanni De Micheli

8 (Africa, Europe, Middle East)

Website

Biography

Giovanni De Micheli is a research scientist in electronics and computer science. He is credited for the invention of the Network on Chip design automation paradigm and for the creation of algorithms and design tools for Electronic Design Automation (EDA). He is a Professor and Director of the Integrated Systems Laboratory at EPFL Lausanne, Switzerland. Previously, he was a Professor of Electrical Engineering at Stanford University. He was Director of the Electrical Engineering Institute (IEL) at EPFL from 2008 to 2019 and program leader of the Swiss Federal Nano-Tera.ch program. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), an M.S., and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).

Prof. De Micheli is a Fellow of ACM, AAAS, and IEEE, a member of the Academia Europaea, and an International Honorary member of the American Academy of Arts and Sciences. His current research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is the author of Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of ten other books and of over 900 technical publications. His citation h-index is above 100 according to Google Scholar. He is a member of the Scientific Advisory Board of IMEC (Leuven, B) and STMicroelectronics.

Prof. De Micheli is the recipient of the 2022 ESDA-IEEE/CEDA Phil Kaufman Award, the 2019 ACM/SIGDA Pioneering Achievement Award, and several other awards.

Affiliation(s)

EPFL

Switzerland

2019

"A Logic Design Structure for LSI Testability"

Proceedings of the 14th Design Automation Conference, pp. 462–468, January 1977

Thomas W. Williams, and Edward B. Eichelberger

For seminal contributions to modern VLSI placement optimization research impacting both academia and industrial practices

2018

"Generic Global Placement and Floorplanning"

Proceedings of the 35th Annual Design Automation Conference, pp. 269-274, June 1998

Hans Eisenmann, and Frank M. Johannes

For seminal contributions to VLSI placement impacting academic and industrial practices

2017

"Chaff: Engineering an Efficient SAT Solver"

Proc. of the 38th annual Design Automation Conference, pp. 530 - 535, June 2001.

Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, and Sharad Malik

Sharad Malik

1 (Northeastern U.S.)

Biography

Sharad Malik (F’02) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India, in 1985, and the M.S. and Ph.D. degrees in computer science from the University of California at Berkeley, Berkeley, CA, USA, in 1987 and 1990, respectively.

He served as the Director of the Keller Center for Innovation in Engineering Education, Princeton University, Princeton, NJ, USA, from 2006 to 2011. He is the George Van Ness Lothrop Professor of Engineering with Princeton University and the Chair of the Department of Electrical Engineering. He has served as the Director of the multi-university MARCO Gigascale Systems Research Center, Berkeley, CA, USA, from 2009 to 2012, and as the Associate Director of the Center for Future Architectures Research, Ann Arbor, MI, USA, from 2013 to 2016. His research in functional timing analysis and propositional satisfiability has been widely used in industrial electronic design automation tools. His current research interest includes design methodology and design automation for computing systems.

Dr. Malik has received the IEEE/ACM Design Automation Conference Award for the most cited paper in the 50-year history of the conference in 2013, the Computer-Aided Verification Award for fundamental contributions to the development of high-performance Boolean satisfiability solvers in 2009, the IEEE/ACM International Conference on Computer-Aided Design Ten Year Retrospective Most Influential Paper Award in 2011, the IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation in 2017, the Princeton University Presidents Award for Distinguished Teaching in 2009, the IIT Delhi Distinguished Alumni Award in 2009, as well as several other research and teaching awards. He is a fellow of the ACM.

Affiliation(s)

Princeton University

United States

For seminal contributions to scalable Boolean satisfiability solving including locality-based search and efficient backtracking.

2016

"First-Order Incremental Block-Based Statistical Timing Analysis"

Proc. of the 41st Design Automation Conference, pp. 331 – 336, June 2004.

Chandu Visweswariah, Kaushik Ravindran, Kerim Kalafala, Steven G. Walker, and Sambasivan Narayan

2015

"Silicon Physical Random Functions"

Proc. of the 9th ACM Conference on Computer and Communications Security, 2002

Blaise Gassend, Dwaine Clarke, Marten van Dijk, and Srini Devadas

2014

"X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction"

IEEE International Test Conference, October 2002

Subhasish Mitra

6 (Western U.S.)

Biography

Subhasish Mitra is currently a Professor of Electrical Engineering and Computer Science at Stanford University, Stanford, CA, USA, where he directs the Stanford Robust Systems Group and co-leads the computation focus area of the Stanford SystemX Alliance. He is also a Faculty Member with the Neurosciences Institute, Stanford University. He holds the Carnot Chair of Excellence in Nanosystems at CEA-LETI, Grenoble, France. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation, Santa Clara, CA, USA. His current research interests include broadly across robust computing, nanosystems, VLSI design, validation, test, and electronic design automation, and neurosciences. He along with his students and collaborators demonstrated the first carbon nanotube computer and the first 3-D nanosystem with computation immersed in data storage. These demonstrations received widespread recognitions (cover of Nature, Research Highlight to the U.S. Congress by the National Science Foundation, highlight as “important, scientific breakthrough” by the BBC, The Economist, Electronic Engineering Times, IEEE Spectrum, MIT Technology Review, National Public Radio, The New York Times, Scientific American, Time, The Wall Street Journal, The Washington Post, and numerous others worldwide). His earlier work on X-Compact test compression has been a key to cost-effective manufacturing and high-quality testing of almost all electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial electronic design automation tools. He is a Fellow of the Association for Computing Machinery (ACM) and IEEE. He received the Association for Computing Machinery Special Interest Group on Design Automation/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation (a test-of-time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel's highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He along with his students published several award-winning papers at major venues, including the ACM/IEEE Design Automation Conference, the IEEE International Solid-State Circuits Conference, the ACM/IEEE International Conference on Computer-Aided Design, the IEEE International Test Conference, the IEEE Transactions on Computer-Aided Design, the IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. He was honored several times by graduating seniors for being important to them during their time at Stanford. He has served on the Defense Advanced Research Projects Agency's Information Science and Technology Board as an Invited Member.

Affiliation(s)

Stanford University

United States

, and Kee Sup Kim

2013

"FastCap: a Multipole Accelerated 3-D Capacitance Extraction Program"

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, November 1991

Keith Nabors, and Jacob K. White

Recipients

2022

"Efficient Steady-State Analysis based on Matrix-Free Krylov-Subspace Methods"

2021

"Transition Fault Simulation"

2020

"Networks on Chips: A New SoC Paradigm"

2019

"A Logic Design Structure for LSI Testability"

2018

"Generic Global Placement and Floorplanning"

2017

"Chaff: Engineering an Efficient SAT Solver"

2016

"First-Order Incremental Block-Based Statistical Timing Analysis"

2015

"Silicon Physical Random Functions"

2014

"X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction"

2013

"FastCap: a Multipole Accelerated 3-D Capacitance Extraction Program"

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