CAD for Assurance

The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner, with an easy-to-search and easy-to-access interface. We’re including information on many major CAD tools the research community has developed over the past decade, including open-source license-free or ready-for-licensing tools, associated metrics, relevant publications, and video-demos.

We are delighted to continue the series of virtual CAD for Assurance tool training webinars that started in February 2021. Additional information on these webinars is available at the CAD for Assurance website at https://cadforassurance.org/.

If you are interested in receiving updates and emails about future CAD for Assurance webinars, please signup using this form http://eepurl.com/hxTwWf.

Webinars

Date/Time (EST)	Title	Speakers/Moderators Panelists	CAD Tools	Registration	Recordings
FRI. FEB 12, 2021 11:00AM-12:20PM EST	NETA Toolset 30-min demo with a 10-min Q&A	Travis Meade (UCF)	LINK	🌐 Zoom	📺 Webinar
FRI. FEB 12, 2021 11:00AM-12:20PM EST	FEDS, SAFARI, XFC 30-min demo with a 10-min Q&A	Chester Rebeiro (IIT Madras)	LINK 1 LINK 2 LINK 3	🌐 Zoom	📺 Webinar
FRI. MAR 12, 2021 11:00AM-12:20PM EST	RTL Logic Attacks 30-min demo with a 10-min Q&A	Chandan Karfa (IIT Guwahati)	LINK	🌐 Zoom	📺 Webinar
FRI. MAR 12, 2021 11:00AM-12:20PM EST	SMT Attack 30-min demo with a 10-min Q&A	Avesta Sasan (GMU)	LINK	🌐 Zoom	📺 Webinar
MON. APR 19, 2021 11:00AM-12:20PM ET	Panel 1: Microelectronics Assurance Under Zero Trust Model Download Flyer: PDF \| PPT	Moderators: Saverio Fazzari (BAH) Panelists: - Rob Aitken, ARM - Brian Dupaix, AFRL - Matt French, ISI/USC - James Wilson, DARPA		🌐 Zoom	Panel presentations and discussions were not recorded.
FRI. MAY 14, 2021 11:00AM-12:20PM ET	Deep Learning-Based Model Building Attacks on Arbiter PUF Compositions 30-min demo with a 10-min Q&A	Rajat Subhra Chakraborty (IIT Kharagpur) Pranesh Santikellur (IIT Kharagpur)	LINK	🌐 Zoom	📺 Webinar
FRI. MAY 14, 2021 11:00AM-12:20PM ET	NEOS Toolset 30-min demo with a 10-min Q&A	Kaveh Shamsi (UT-Dallas)	LINK	🌐 Zoom	📺 Webinar
FRI. JUN 11, 2021 11:00AM-12:20PM ET	Side-Channel Analysis 30-min demo with a 10-min Q&A	Debdeep Mukhopadhyay (IIT Kharagpur)	LINK	🌐 Zoom	📺 Webinar
FRI. JUN 11, 2021 11:00AM-12:20PM ET	MIMI 30-min demo, 10-min Q&A	Patanjali SLPSK and Jonathan Cruz (UF)	LINK	🌐 Zoom	📺 Webinar
FRI. JUL 9, 2021 11:00AM-12:20PM ET	Panel 2: Side-channel leakage - Can CAD come to the rescue?	Moderator: Patrick Schaumont (WPI) Panelists: - Serge Leef, DARPA - Jasper van Woudenberg, Riscure - Colin O’Flynn, NewAE - Francesco Regazzoni , U Amsterdam		🌐 Zoom	📺 Webinar
FRI. AUG 13, 2021 11:00AM-12:20PM ET	Malware Detectors 30-min demo, 10-min Q&A	Kanad Basu (UT Dallas)	LINK	🌐 Zoom	📺 Webinar
FRI. AUG 13, 2021 11:00AM-12:20PM ET	Introduction to Common Evaluation Platform (CEP) 30-min demo, 10-min Q&A	Brendon Chetwynd (MIT Lincoln Lab)	LINK	🌐 Zoom	📺 Webinar
FRI. SEPT 10, 2021 11:00AM-12:20PM ET	Hands-on Hardware Assurance: Demos of Select Experiments on a Flexible Training Platform 60-min demo, 10-min Q&A	Reiner Dizon and Christopher Vega (UF)		🌐 Zoom	📺 Webinar
FRI. OCT 8, 2021 11:00AM-12:20PM ET	Panel 3: Security Assessment and Verification for Microelectronics - A New Future or More of the Same? 80-min panel	Moderator: Sandip Ray (UF) Panelists: - Kevin Bush (MIT Lincoln Lab) - Sharad Malik (Princeton U) - Keith Rebello (Darpa) - Robert B. Jones (Intel) - Jamin McCue (AFRL)		🌐 Zoom	📺 Webinar
FRI. NOV 5, 2021 11:00AM-12:20PM ET	SeqL: Scan Chain Locking and a Broad Security Evaluation 30-min demo, 10-min Q&A	Seetal Potluri (NC State University) Aydin Aysu (NC State University)	LINK	🌐 Zoom	📺 Webinar
FRI. NOV 5, 2021 11:00AM-12:20PM ET	Protecting against Untrusted COTS 30-min demo, 10-min Q&A	Tamzidul Hoque (University of Kansas)	LINK	🌐 Zoom	📺 Webinar
FRI. FEB 18, 2022 11:00AM-12:20PM ET	SAIL: Machine Learning Attack on Logic Locking and Obfuscation 30-min demo, 10-min Q&A	Prabuddha Chakraborty (UF)	LINK 1 LINK 2	🌐 Zoom	📺 Webinar
FRI. FEB 18, 2022 11:00AM-12:20PM ET	PLAN: Power Side-Channel Evaluation 30-min demo, 10-min Q&A	Ayalur Lakshmy and Chester Rebeiro (IIT Madras)	LINK 1 LINK 2	🌐 Zoom	📺 Webinar
FRI. APR 22, 2022 11:00AM-12:20PM ET	QFlow: Quantifying Data Leakage for RTL IP 30-min demo, 10-min Q&A	Lennart Reimann (RWTH Aachen University)	LINK 1	🌐 Zoom	📺 Webinar
FRI. APR 22, 2022 11:00AM-12:20PM ET	QIF-RTL: A New Secure Hardware Description Language 30-min demo, 10-min Q&A	Xiaolong Guo (Kansas State University)	LINK 2	🌐 Zoom	📺 Webinar
FRI. JUN 10, 2022 11:00AM-12:20PM ET	Panel 4: Securing Crypto in the Pre & Post-Quantum Era: Opportunities and Challenges? 80-min panel	Moderator: Debdeep Mukhopadhyay (IIT Kharagpur) Panelists: - Rosario Cammarota, Intel - Ramesh Karri, New York University - Sri Parameswaran, UNSW Sydney - Apostol Vassilev, NIST - Ingrid Verbauwhede, KU Leuven		🌐 Zoom
FRI. AUG 12, 2022 11:00AM-12:20PM ET	Panel 5: Hardware Assurance vs. AI: Friend or Foe? 80-min panel	Moderators: Ankur Srivastava (U. of Maryland) and Swarup Bhunia (U. of Florida)		🌐 Zoom
FRI. OCT 07, 2022 11:00AM-12:20PM ET	DANA: Universal Data Flow Analysis for Gate-Level Netlist Reverse Engineering 30-min demo, 10-min Q&A	Nils Albartus (Ruhr University Bochum)	LINK 1	🌐 Zoom
	Hardware Trojan Benchmarks: From Chips to PCB 30-min demo, 10-min Q&A	Jonathan Cruz (University of Florida)	LINK 2

Registration

Registration for the webinars is required. Please select the Zoom session for each webinar you wish to attend. For questions, please contact the organizers.

Organizers

Swarup Bhunia

University of Florida

United States

3 (Southeastern U.S.)

Gang Qu

University of Maryland

United States

2 (Eastern U.S.)

Tsung-Yi Ho

National Tsing Hua University

Taiwan

10 (Asia and Pacific)

Tsung-Yi Ho

10 (Asia and Pacific)

Biography

Tsung-Yi Ho (SM’10) received the Ph.D. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2005. He is a Professor with the Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. He has presented ten tutorials and contributed 11 special sessions in ACM/IEEE conferences, all in design automation for microfluidic biochips. His research interests include design automation and test for microfluidic biochips and nanometer integrated circuits.

Dr. Ho is the recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science, the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, and the Hans Fischer Fellowship by the Institute of Advanced Study, Technical University of Munich. He was a recipient of the Best Paper Awards at the VLSI Test Symposium in 2013 and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2015. He served as a Distinguished Visitor of the IEEE Computer Society for 2013–2015, the Chair of the IEEE Computer Society Tainan Chapter for 2013–2015, and the Chair of the ACM SIGDA Taiwan Chapter for 2014–2015. He is currently an ACM Distinguished Speaker, a Distinguished Lecturer of the IEEE Circuits and Systems Society, and an Associate Editor for the ACM Journal on Emerging Technologies in Computing Systems, the ACM Transactions on Design Automation of Electronic Systems, the ACM Transactions on Embedded Computing Systems, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and the Technical Program Committees of major conferences, including the Design Automation Conference, the International Conference on Computer-Aided Design, the IEEE/ACM Design Automation and Test in Europe Conference, the Asia and South Pacific Design Automation Conference, the ACM/SIGDA International Symposium on Physical Design, and the International Conference on Computer Design.

Affiliation(s)

National Tsing Hua University

Taiwan

Yier Jin

University of Florida

United States

3 (Southeastern U.S.)

Yier Jin

3 (Southeastern U.S.)

Biography

Yier Jin is the Endowed IoT Term Professor in the Warren B. Nelms Institute for the Connected World and also an Associate Professor in the Department of Electrical and Computer Engineering (ECE) in the University of Florida (UF). Prior to joining UF, he was an assistant professor in the ECE Department at the University of Central Florida (UCF). He received his PhD degree in Electrical Engineering in 2012 from Yale University after he got the B.S. and M.S. degrees in Electrical Engineering from Zhejiang University, China, in 2005 and 2007, respectively. His research focuses on the areas of embedded systems design and security, trusted hardware intellectual property (IP) cores and hardware-software co-design for modern computing systems. He is currently focusing on the design and security analysis on Internet of Things (IoT) and wearable devices with particular emphasis on information integrity and privacy protection in the IoT era. Dr. Jin received Young Investigator Grant from Southeastern Center for Electrical Engineering Education (SCEEE) in 2015, early CAREER award from Department of Energy (DoE) in 2016, Outstanding New Faculty Award (ONFA) from ACM’s Special Interest Group on Design Automation (SIGDA) in 2017, and Young Investigator Award (YIP) from Office of Naval Research (ONR) in 2019. He also received the Best Paper Award of the 52nd Design Automation Conference in 2015, the 21st Asia and South Pacific Design Automation Conference (DAC) in 2016, the 10thIEEE Symposium on Hardware-Oriented Security and Trust (HOST) in 2017, the 2018 ACM Transactions on Design Automation of Electronic Systems (TODAES), the 28thedition of the ACM Great Lakes Symposium on VLSI (GLSVLSI) in 2018, and the Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2019. He is the IEEE Council on Electronic Design Automation (CEDA) Distinguished Lecturer.

Affiliation(s)

University of Florida

United States