To recognize the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Historical Background: The IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award is sponsored by the IEEE Council on EDA and recognizes the best paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems publication. The award is based on the overall quality, the originality, the level of contribution, the subject matter and the timeliness of the research. Anyone who is an author of a paper published in the Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award is eligible for nomination. Prize: $500 for each author (maximum of $2,000 per award) and certificate Funding: Funded by the IEEE Council on Electronic Design Automation. Presentation: The award will be presented at the ICCAD conference. Basis for Judging: General quality, originality, contributions, subject matter, and timeliness. Eligibility: Authors of papers published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems during the two calendar years preceding the award. Self Nominations are permitted. Each nominator may only nominate one paper only. Nomination Details: The nomination deadline is 28 February of the award year. Nomination Form: Nominate for this Award Recipients 2005 "X-compact: An Efficient Response Compaction Technique" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 3, pp. 421-432, March 2004 Subhasish Mitra, and Kee Sup-Kim Acceptance Speech × 2004 "Synthesis of Reversible Logic Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, Issue 6, pp. 710-722, June 2003 Vivek V. Shende, Aditya K. Prasad, and John P. Hayes Acceptance Speech × 2003 "An Efficient Graph Representation for Arithmetic Circuit Verification" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Issue 12, pp. 1443-1454, December 2001 Yirng-An Chen, and Randal E. Bryant Acceptance Speech × 2002 "Floorplanning Using a Tree Representation" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Issue 2, February 2001 Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, and Takeshi Yoshimura Acceptance Speech × 2001 "SPFD: A New Method to Express Functional Flexibility" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, Issue 8, pp. 840-849, August 2000 Shigeru Yamashita, Hiroshi Sawada, and Akira Nagoya Acceptance Speech × 2000 "A Quadratic Programming Approach to Simultaneous Buffer Insertion/Sizing and Wire Sizing" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, Issue 6, pp. 787-798, June 1999 Chris Chu, and Martin D.F.Wong Acceptance Speech × 1999 "PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, Issue 8, pp. 645-654, August 1998 Altan Odabasioglu, Mustafa Celik, and Larry Pileggi Acceptance Speech × Pagination « First First page ‹‹ Previous page 1 2 3
"X-compact: An Efficient Response Compaction Technique" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 3, pp. 421-432, March 2004
"Synthesis of Reversible Logic Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, Issue 6, pp. 710-722, June 2003
"An Efficient Graph Representation for Arithmetic Circuit Verification" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Issue 12, pp. 1443-1454, December 2001
"Floorplanning Using a Tree Representation" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Issue 2, February 2001
"SPFD: A New Method to Express Functional Flexibility" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, Issue 8, pp. 840-849, August 2000
"A Quadratic Programming Approach to Simultaneous Buffer Insertion/Sizing and Wire Sizing" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, Issue 6, pp. 787-798, June 1999
"PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, Issue 8, pp. 645-654, August 1998