CAD for Assurance: Panel 6: Hardware Security 2.0: What Are The New Frontiers?

Register for the next CAD for Assurance webinar.

Topic: Panel 6: Hardware Security 2.0: What Are The New Frontiers?

Date: Friday, 24 February 2023

Time: 11:00AM-12:30PM ET

Panelists:

-David Kehlet, Intel

-Murthi Sadhasivan, Aerospace Corporation

-Serge Leef, Microsoft

-Rainer Leupers, RWTH Aachen University

-Chip Hong Chang, Nanyang Technological University

Abstract:

For the past decade and a half, the hardware security community has dedicated significant time and attention towards the threats related to semiconductor globalization. With the passage of the CHIPS Act in the US and similar legislation in Europe, it is time to reconsider intellectual property (IP) protection and assurance in a new context. For instance, physical attacks, such as side-channel attacks, fault-injection attacks, optical probing, and reverse engineering, now pose the greater threat to security, trust, assurance, and privacy. In parallel, the chip design and computing landscapes are shifting in order to compensate for losses in energy efficiency, performance, area, cost, etc. due to the end of Moore’s Law. Key enabling technologies include heterogeneous integration, multi-chiplet architectures, in-memory computing, and multi-tenancy. This panel will discuss these recent trends, debate their positive and negative impacts on hardware security, and forecast the new frontiers to be explored by the hardware community.

Register