Cyber-physical systems (CPS), such as automotive, manufacturing, and power grid systems, are engineered systems built from and depend upon the seamless integration of computation and physical components. Embedded systems comprising of hardware and software systems are the primary enabling technology for these cyber-physical systems. Moreover, when cyber-physical systems get connected to the Internet, it forms the Internet-of-Things (IoT). Today, CPSs can be found in security-sensitive areas such as aerospace, automotive, energy, healthcare, manufacturing transportation, entertainment, and consumer appliances. Compared to the traditional information processing systems, due to the tight interactions between cyber and physical components in CPSs and closed-loop control from sensing to actuation, new vulnerabilities emerge from the boundaries between various layers and domains. In this seminar, Dr. Al Faruque will discuss how new vulnerabilities emerge at the intersection of multiple components and subsystems and their different hardware, software, and physical layers. Several recent examples from various cyber-physical systems (e.g., an automotive system) will be presented in this talk. To understand these new vulnerabilities, a very different set of methodologies and tools are needed. Defenses against these vulnerabilities also demand new hardware/software co-design approaches. The seminar will highlight recent developments in this regard. This seminar's primary goal will be to highlight various research challenges and the need for novel scientific solutions from the EDA research community and definitely from the larger embedded systems, cyber-physical systems, distributed computing systems, and computer architecture research communities.

Over the years, design automation methodologies have been employed to alleviate the extensive task of manual system design across the different levels of abstraction, as in the EDA, Embedded, and Cyber-Physical Systems (CPS) domains. As Deep Learning (DL) becomes the enabling technology of today's intelligent applications, design automation methodologies have found their way into the DL field through techniques like Neural Architecture Search (NAS). Such methods are providing high-performing neural architecture models compared to the manually designed ones. Yet, driven by the application requirements of real-time inference and computation efficiency, the current design tendency is to push the computation to the edge of the network itself, be it on the user's end devices or the network gateways. Consequently, device specifications, application characteristics, and computing paradigms must be integrated within the design automation methodologies. Therefore, sophisticated techniques are needed to capture the interacting dynamics of the different system components in terms of compute capabilities, resource utilization, and intra-system communication. In this seminar, Dr. Al Faruque will discuss how to implement design automation methodologies for DL applications, tuned to the different requirements of modern smart edge-AI systems. He will present several examples ranging from low-power wearable devices to compute-intensive Autonomous Vehicles. Moreover, this seminar will highlight how the emerging split computation and early-exit computing can be incorporated into the design optimization aspect to provide AI-enabled edge systems for different applications.

Embedded systems comprising hardware and software systems are the primary enabling technology for modern cyber-physical systems such as home devices, autonomous vehicles, and industrial manufacturing machines. The global embedded system market is estimated to grow from 86 billion dollars to 116 billion dollars by 2025. This phenomenon also reveals that these systems can now or in the future generate a considerable amount of data, so making good use of these data has become very important in this field. Conventional machine learning only applies to the data in the Euclidean form, while in practice, more and more data appears as non-Euclidean data such as graphs, manifolds, etc. To use these ML models, researchers have to manually engineer features from these non-Euclidean data with their expertise in the field and spend efforts in tuning them to avoid the loss of information from original data. In this case, Graph Learning techniques have become increasingly important as they can bypass this step and directly process the graph data. In this seminar, Dr. Al Faruque will discuss how to apply graph learning techniques to different applications for embedded systems. This talk will mainly present the approaches leveraging graph learning for Autonomous Driving Systems (ADSs), hardware security, and software security. In ADSs, recent work by Dr. Al Faruque leverages scene-graph as an intermediate representation to better understand the driving scenes and infer the level of riskiness for actions. In hardware security, Dr. Al Faruque’s group utilizes graph representations of hardware designs, such as abstract syntax trees (ASTs) or control-flow graphs (CFGs), and graph learning approaches to solve hardware security problems (hardware trojan detection/IP piracy detection) at the behavioral level.

The steady rise of intelligence and autonomy over a scale of distributed, connected and smart components is heralding the era of Internet-of-Intelligence. Without adequate safeguards in place, such components can lead to terrible consequences. In this talk, I will discuss three topics - namely, vulnerability, design for security and privacy of such edge–computing scenarios. The vulnerability aspect will be demonstrated through multiple attacks that we conducted, using practical case studies on edge devices. The design for security perspective will be discussed, first, through system-level security-by-design methodologies; second, through efficient lightweight cryptographic accelerator designs and design automation flows; third, through automation of attack/prevention techniques. Finally, the privacy perspective will be presented through an innovative tunable compression technique, realized on top of a video/image-processing platform.

The continued scaling of horizontal and vertical physical features of silicon-based complementary metal-oxide-semiconductor (CMOS) transistors, termed as “More Moore”, has a limited runway and would eventually be replaced with “Beyond CMOS” technologies. There has been a tremendous effort to follow Moore’s law but it is currently approaching atomistic and quantum mechanical physics boundaries. This has led to active research in other non-CMOS technologies such as memristive devices, carbon nanotube field-effect transistors, quantum computing, etc. Several of these technologies have been realized on practical devices with promising gains in yield, integration density, runtime performance, and energy efficiency. Their eventual adoption is largely reliant on the continued research of Electronic Design Automation (EDA) tools catering to these specific technologies. Indeed, some of these technologies present new challenges to the EDA research community, which are being addressed through a series of innovative tools and techniques. In this tutorial, we will particularly cover the two phases of EDA flow, logic synthesis, and technology mapping, for two types of emerging technologies, namely, in-memory computing and quantum computing.

The rise of AI and in particular, deep learning (DL), is a key driver for innovations in computing systems. There is a significant effort towards the design of custom accelerator chips based on reduced precision arithmetic and highly optimized data flow. However, the need to shuttle millions of synaptic weight values between the memory and processing units remains unaddressed. In-memory computing (IMC) is an emerging computing paradigm that addresses this challenge of processor-memory dichotomy. Attributes such as synaptic efficacy and plasticity can be implemented in place by exploiting the physical attributes of memory devices such as phase-change memory (PCM). In this talk, I will give a status update on where in-memory computing stands with respect to DL acceleration. I will present some recent algorithmic advances for performing accurate DL inference and training with imprecise IMC. I will also present state-of-the-art IMC compute cores based on PCM fabricated in 14nm CMOS technology and touch upon some systems-level aspects. Finally, I will present some applications of IMC that transcend conventional DL such as memory-augmented neural networks and spiking neural networks.

Traditional computing systems involve separate processing and memory units. However, data movement is costly in terms of time and energy and this problem is aggravated by the recent explosive growth in highly data-centric applications related to artificial intelligence. This calls for a radical departure from the traditional systems and one such computational approach is in-memory computing. Hereby certain computational tasks are performed in place in the memory itself by exploiting the physical attributes of the memory devices. In this lecture, I will give an overview of the primary charge-based and resistance-based Seminar Titles (Maximum 3) memory devices being explored for in-memory computing as well as the key computational primitives they enable. Subsequently, I will present an overview of the key applications of in-memory computing that span scientific computing, signal processing, optimization, machine learning, deep learning, and stochastic computing.

In the past a few years, powered by the strong need of edge intelligence, there has been an increasing interest in deploying deep neural networks on tiny hardware with limited computing power and energy (tinyML). A fundamental question needs to be addressed: given a specific edge intelligence task, what is the optimal neural architecture and the tailor-made hardware in terms of accuracy and efficiency? Earlier approaches attempted to address this question through hardware-aware neural architecture search (NAS), where fa fixed hardware design such as microcontrollers or light-weight CPUs are taken into consideration when designing neural architectures. However, we believe that the most powerful and elegant solutions should come from hardware that allows customization, such as FPGAs, ASICs, or Computing-in-Memory accelerators. For these platforms, we are the first to establish the concept of software/hardware co-design, which simultaneously explore neural architecture and the hardware design to identify the best pairs that maximize both test accuracy and hardware efficiency. In this talk, we will present the novel co-exploration frameworks for neural architecture and various hardware platforms including FPGA, ASIC and Computing-in-Memory, all of which are the first in the literature. We will demonstrate that our co-exploration concept greatly opens up the design freedom and pushes forward the Pareto frontier between hardware efficiency and test accuracy for better design tradeoffs in tinyML.

Despite the pursuit of quantum advantages in various applications, the power of quantum computers in executing neural network has mostly remained unknown, primarily due to a missing tool that effectively designs a neural network suitable for quantum circuit. In this talk, I will present our open-source neural network and quantum circuit co-design framework, namely QuantumFlow, to address the issue. In QuantumFlow, we represent data as unitary matrices to exploit quantum power by encoding n = 2k inputs into k qubits and representing data as random variables to seamlessly connect layers without measurement. Coupled with a novel algorithm, the cost complexity of the unitary matrices-based neural computation can be reduced from O(n) in classical computing to O(polylog(n)) in quantum computing. I will further demonstrate the results on MNIST dataset using IBM quantum processors, which show that QuantumFlow can achieve an accuracy of 94.09% with a cost reduction of 10.85 × against the classical computer. This is the first time that quantum advantage is demonstrated practically on the inference of deep neural networks, and the tool has been accessed over 1,200 times within its first month of release.

With the prevalence of deep neural networks, machine intelligence has recently demonstrated performance comparable with, and in some cases superior to, that of human experts in medical imaging and computer assisted intervention. Such accomplishments can be largely credited to the ever-increasing computing power, as well as a growing abundance of medical data. As larger clusters of faster computing nodes become available at lower cost and in smaller form factors, more data can be used to train deeper neural networks with more layers and neurons, which usually translate to higher performance and at the same time higher computational complexity. For example, the widely used 3D U-Net for medical image segmentation has more than 16 million parameters and needs about 4.7×1013 floating point operations to process a 512×512×200 3D image. The large sizes and high computation complexity of neural networks have brought about various issues that need to be addressed by the joint efforts between hardware designers and medical practitioners towards hardware aware learning. In this talk, I will present novel solutions for the data acquisition and data processing stages in medical image computing respectively, using hardware-oriented schemes for lower latency, memory footprint and higher performance in embedded platforms. I will discuss how our hardware-aware machine learning approaches led to the realtime MRI segmentation for prosthetic valve implantation assistance, and enabled the world’s first AI assisted telementoring of cardiac surgery on April 3, 2019.

Recently machine learning, especially deep learning is gaining much attention due to the breakthrough performance in various cognitive tasks. Machine learning for electronic design automation is also gaining traction as it provides new techniques for many of the challenging design automation problems with complex nature. Thermal and power modeling and online regulation for many-core and embedded systems have been intensively studied in the past. But real-time full-chip thermal estimation for commercial multi-core processors is still a challenging problem. In this talk, I will first show that one can build an accurate transient thermal map of commercial off-the-shelf multi-core microprocessors based on the given on-chip sensors and real-time utilization information based on a data-driven deep learning-based approach. The new models are directly based on the available real-time high-level chip utilization and thermal sensor information of commercial chips without any assumption of additional physical sensors requirements. I will explore different deep learning neural networks (DNN) architectures such as recurrent neural networks and generative adversarial networks and show how to frame the full-chip thermal map learning problems as the supervised data-driven learning processes for those DNN networks for commercial many-core processors. Our work is further enabled by an infrared thermography system, which can provide lucid thermal maps of commercial multi-core CPUs and many-core GPUs while nominal working conditions are maintained on the chip. 

As machine learning, especially deep learning, has been proved to be effective for capturing spatial and temporal dynamics behaviors, it brings new opportunities for addressing those difficult tasks. In this talk, I will look at the emerging machine learning/deep learning-based approaches for the VLSI interconnect reliability modeling, optimization, and dynamic management. I first present a machine learning-based approach to model hydrostatic stress in the multi-segment interconnects based on the generative adversarial learning, in which we treat the stress modeling as a time-varying 2D image-to-image conversion problem and the resulting solution provide an order of magnitudes over existing numerical method and 10x over state of art semi-analytic method. Second, based on the observation that VLSI multi-segment interconnects trees can be naturally viewed as graphs. I will present a new graph convolution network (GCN) model, called EMgraph, to consider both node and edge embedding features, to estimate the transient EM stress of interconnecting trees. The new method can lead 10X speedup over GAN-based EM analysis with transferable knowledge to predict stress on new interconnect trees. To mitigate the long-term aging effects due to NBTI, EM, and HCI, I further present an accuracy reconfigurable stochastic computing (ARSC) framework for dynamic reliability and power management. Different than the existing stochastic computing works, where the accuracy versus power/energy trade-off is carried out in the design time, the new ARSC design can change the accuracy or bit-width of the data in the run-time so that it can accommodate the long-term aging effects by slowing the system clock frequency at the cost of accuracy while maintaining the throughput of the computing.

Electromigration (EM) remains the top killer for the copper-based interconnects in current and near-future advanced VLSI technologies. As the technologies scale, the allowable current density continues to decrease due to EM while the required current density to drive the gates increases. 2015 ITRS predicts that EM lifetime of interconnects of VLSI chips will be reduced by half for each generation of technology nodes. The most important observation from our recent study is that EM analysis needs to consider multi-wire segments in the same metal layer to be more accurate and less conservative for all the advanced deep micro techniques. Existing current density-based EM check can lead to significant over-design and loss of design optimization opportunities. Our lab’s recent mission is to change this widely adopted industry design practice to move into new generation EM modeling, assessment, and design techniques. In this talk, I will present recent research works in my research lab (VSCLAB) at UC Riverside. I will cover newly proposed physics-based electromigration (EM) models, especially the physics-based three-phase EM models and full-chip EM-induced IR drop analysis techniques. I will first present the recently proposed three-phase EM model, which much more accurately describes the EM failure process and post-voiding resistance change phenomena. I then introduce two new EM immortality check methods for general multi-segment interconnect wires, which can be viewed as the Blech Product to multi-branch interconnects. Then I will present a novel fast finite difference method (FDM) for EM stress analysis based on frequency domain model order reduction techniques. On top of this, I will present the recently proposed coupled EM-IR drop analysis tool, EMspice, for full-chip EM-induced IR drop analysis of power delivery networks and show how it integrates with Synopsys ICC design flow. EMspice incorporates the latest EM modeling and analysis techniques for multi-segment interconnects, such as EM immortality checks considering both nucleation and incubation phases, the interaction between IR drop, and EM aging effects in the post-void EM phase, EM recovery effects and temporal temperature effects etc. Last, not least, I will present recent work on EM-aware power grid design and optimization, which exploits the recently developed EM modeling and assessment techniques for multi-segment interconnect wires.

Recently machine learning, especially deep learning is gaining much attention due to the breakthrough performance in various cognitive applications. Machine learning for electronic design automation (EDA) is also gaining significant Tutorial Titles (Maximum 3) traction as it provides new computing and optimization paradigms for many challenging design automation problems with complex nature. Today’s chip designers and EDA developers face several many challenges in advanced technologies from technology and physical levels to the circuit and multi-core chip levels. Given the complex nature of both modeling and online thermal/power/reliability control challenges in advanced technologies from one hand, there are a lot of potentials in using the latest advances in machine learning to tackle those hard problems towards developing intelligent runtime management schemes. In this tutorial, I present several novel machine-learning-based solutions to the after-mentioned EDA challenges. I will first focus on novel full-chip thermal and power map estimation techniques using the recurrent neural networks (RNN) and generative adversarial (GAN) network methods for commercial multi-core processors first. I will show for the first time the new capability of real-time full-chip thermal tracking for commercial microprocessors. I also show how to obtain accurate power density maps and thermal maps for those commercial chips with practical heat sinks for more advanced thermal/power/reliability management. I also present the recent proposed ThermGAN approach, which uses the adverbial generative learning method to estimate the full-chip thermal maps and compared favorably to the existing RNN based methods. For dynamic thermal/reliability management, I will present a recently proposed deep reinforced learning (DRL) based control method based on the reliability of workload-dependent true hotspot identification and modeling of commercial multi-core processors. For electromigration (EM) induced VLSI to interconnect reliability modeling and optimization, I will present the recently proposed EMGraph approach, which applied graph convolutional networks (GCN) to consider both node and edge embedding features, to estimate the transient EM stress of multi-segment interconnect trees.

In this tutorial, I will present some of the recent research works in my research lab (VSCLAB) at UC Riverside. First, I will review a recently proposed physics-based three-phase EM model for multi-segment interconnect wires, which consists of nucleation, incubation, and growth phases to completely model the EM failure processes in typical copper damascene interconnects. The new EM model can predict more accurate EM failure behaviors for multi-segment wires such as interconnects with reservoir and sink segments. Second, I will present newly proposed fast aging acceleration techniques for efficient EM failure detections and validation of practical VLSI chips. I will present the novel configurable reservoir/sink-structured interconnect designs in which the current in the sink segment can be activated/deactivated dynamically during operation. In this way, the stress conditions of the interconnect wires can be increased and the lifetime of the wires can be reduced significantly. Afterward, I will present the compact dynamic EM models for general multi-segment interconnect wires and voltage-based EM immortality check algorithm for general interconnect trees. Then I will present a fast 2D stress numerical analysis technique based on the Krylov subspace and finite difference time domain methods (FDTD) for general interconnect wire’s structure. The proposed numerical analysis method can lead to 100X speedup over the simple FDTD method and can be applied to any interconnect structures for all the EM wear-out phases. Then I will focus on the system-level dynamic reliability management (DRM) techniques based on the newly proposed physics-based EM models. I will show several recent works of the EM-aware DRM for lifetime optimizations for dark-silicon, embedder/real-time systems, and 3D ICs to improve the TSV reliability. Last, not least, I will present the work to consider special temperature gradient impacts on EM due to the Joule heating effect. The spatial temperature gradient induced metal atom migration effects, also called temperature migration (TM), was shown to be as significant as the EM itself as technology advances. In our work, I will show how to consider TM effects in both existing EM immortality check and semi-analytic based approaches for the first time.

Long-term reliabilities such as electromigration (EM) induced failures in integrated circuits are expected to grow rapidly with shrinking feature sizes in new technology nodes and novel solutions to address reliability at different levels. This talk presents a new power grid network design and optimization technique that considers the new EM immortality constraint due to EM void saturation volume for multi-segment interconnects. When a void is formed, it is considered to be a failure in traditional EM models. However, this is quite a conservative assumption as a void may never grow to sufficient volume to make a significant change to the wire resistance. By considering saturation volume for multisegment interconnects wires, we can remove such conservativeness in the EMaware on-chip power grid design. Along with another new proposed immortality constraint for the EM nucleation phase for multi-segment wires, I will show that both EM immortality constraints can be naturally integrated into the existing programming-based power grid optimization framework. To mitigate the overly conservative nature of the optimization formulation, I will further explore two strategies: first, we size up failed wires to meet one of the immortality conditions subject to design rules; second, I will consider the EM-induced aging effects on power supply networks for a target lifetime, which allows some short-lifetime wires to fail and optimizes the rest of the wires. Last, not least, I will present our recent work using deep neural networks to model the full-chip EM-induced IR drop and leveraging of the differential feature of DNN for fast sensibility calculation for sensitivity-guided full-chip EM-aware power grid optimization. 

Hardware has long been touted as a dependable and trustable entity than the software running on it. The illusion that attackers cannot easily access the isolated integrated circuit (IC) supply chain has once and again been invalidated by remotely activated hardware Trojan and untraceable break-ins of networking systems running on fake and subverted chips reported by businesses and military strategists, and confirmed by forensic security experts analyzing recent incidents. The situation was aggravated by the geographical dispersion of chip design activities and the heavy reliance on third-party hardware intellectual properties (IPs). Counterfeit chips (such as unauthorized copies, remarked/recycled dice, overproduced and subverted chips or cloned designs) pose a major threat to all stakeholders in the IC supply chain, from designers, manufacturers, system integrators to end users, in view of the severe consequence of potentially degraded quality, reliability and performance that they caused to the electronic equipment and critical infrastructure. Unfortunately, tools that can analyze the circuit netlist for malicious logic detection and full functionality recovery are lacking to prevent such design backdoors, counterfeit and malicious chips from infiltrated into the integrated circuit (IC) design and fabrication flow. This seminar addresses and reviews recent development in preventive countermeasures, post-manufacturing diagnosis techniques, and emerging security-enhanced primitives to avert these hardware security threats. This seminar also covers emerging topics where hardware platforms are playing an active role in system protection and intrusion detection. It aims to create an awareness of the ultimate challenges and solutions in addressing hardware security issues in the new age of the Internet of Things (IoT), where the intense interactions between devices and devices, and devices and humans have introduced new vulnerabilities of embedded devices and integrated electronic systems. 

Internet of Things (IoT) has become prevalent in everyday life. These sensor-loaded devices are capable of collecting and processing information on their surroundings and transmitting them to remote locations. Harmless as it may seem, this new breed of devices have raised a number of privacy and security concerns. Device manufacturers are becoming increasingly aware of the ensuing complications and backslash an insecure device may have in the infrastructure. Security issues may come at different levels, from deployment issues that leave devices exposed to the internet with default credentials, to implementation issues where manufacturers incorrectly employ existing protocols or develop proprietary ones for communications that have not been examined for their sanity. On the hardware side, a device may also be vulnerable. An attacker with physical access to a device may be able to alter its functionality. A compromised device, whether by remote or physical access means, can then be used as a tool to exfiltrate sensitive network information, attack other devices, and as means of automatically sending malware over the internet. 

Cyber-physical systems (CPS) comprise the backbone of national critical infrastructures such as power grids, transportation systems, home automation systems, etc. Because cyber-physical systems are widely used in these applications, the security considerations of these systems should be of very high importance. While the security concerns of CPS can be divided into different layers with unique challenges in each layer, we will introduce the security vulnerabilities as well as potential countermeasures from the hardware perspective. We will provide detailed examples of our experimentation with CPS devices with emphasis on smart meters and PLC devices. We will then present solutions that have been proposed by both industry and academia. 

Besides the introduction to the IoT and CPS security, hands-on labs are also prepared for all audience. Customized smart devices will be provided where audiences can practice on how to design a commercial/industrial IoT/CPS devices and, more importantly, how to identify the security vulnerabilities of modern connected smart devices as well as how to exploit these vulnerabilities. Potential solutions to secure these devices will also be implemented in the hands-on labs. 

Tutorial table of contents (bulleted list): 

• Introduction to IoT and wearable devices: what is an IoT device? 
• Introduction to CPS: what is a CPS device? 
• Challenges in manufacture: a vendor's view. 
• Pitfalls and roadblocks: what is often overlooked? 
• Security architectures for smart devices 
• Hands-on Module I: IoT device designs 
• Hands-on Module II: IoT security vulnerability exploitation 
• Hands-on Module III: IoT security patches 

Within the past decade, the number of IoT devices introduced in the market has increased dramatically. The total is approaching a staggering 15 billion, meaning that there are currently roughly two connected devices per living human. However, the massive deployment of IoT devices has led to significant security and privacy concerns given that security is often treated as an afterthought for IoT systems. Security issues may come at different levels, from deployment issues that leave devices exposed to the internet with default credentials, to implementation issues where manufacturers incorrectly employ existing protocols or develop proprietary ones for communications that have not been examined for their sanity. While existing cybersecurity and network security solutions can help protect IoT, they often suffer from limited onboard/on-chip resources. To mitigate this problem, researchers have developed multiple solutions based on a top-down (relying on the cloud for IoT data processing and authentication) or a bottom-up (leveraging hardware modifications for efficient cybersecurity protection). In this talk, I will first introduce the emerging security and privacy challenges in the IoT domain. I will then focus on the bottom-up solutions on IoT protection and will present our recent research effort in microarchitecture supported IoT runtime attack detection and device attestation. The developed methods will lead to a design-for-security flow towards trusted IoT and their applications.

As semiconductor technology enters the sub-14nm era, geometry, process, voltage and temperature (PVT) variability in devices can affect the performance, functionality, and power of circuits, especially in new Artificial Intelligent (AI) accelerators. This is where predictive failure analytics is extremely critical. It can identify the failure issues related to logic and memory circuits and drive the circuits in the energy efficient area. 

This talk describes how key statistical techniques and new algorithms can be effectively used to analyze and build robust circuits. These algorithms can be used to analyze decoders, latches, and volatile as well as non-volatile memories. In addition, how these methodologies can be extended to “reliability prediction” and “hardware corroboration” is demonstrated. Logistic regression-based machine learning techniques are employed for modeling the circuit response and speeding up the importance of sample points simulations. To avoid overfitting, a cross-validation based regularization framework for ordered feature selection is demonstrated. Also, techniques to generate accurate parasitic capacitance modeling along with PVT variations for sub-22nm technologies and their incorporation into a physics-based statistical analysis methodology for accurate Vmin analysis are described. In addition, extension of these techniques based on machine learning e.g KNN is highlighted. Finally, the talk summarizes important issues in this field. 

Moore’s law driving the advancement in the semiconductor industry over decades has been coming to a screeching halt and many researchers are convinced that it is almost dead. After revival and promise of artificial intelligence (AI) due to increased computational performance and memory bandwidth aided by Moore’s law, there is overwhelming enthusiasm in researchers for increasing the pace of VLSI industry. AI uses many neural network techniques for computation which involves training and inference. The advancement in AI requires energy efficient, low power hardware systems. This is more so for servers, main processors, Internet of Things (IoT) and System on chip (SOC) applications and newer applications in cognitive computing. 

In the light of AI, this talk focuses on important circuit techniques for lowering power, improving performance and functionality in nanoscale VLSI design in the midst of variability. The same techniques can be used for AI specific accelerators. Accelerator development for reduction in power and throughput improvement for both edge and data-centric accelerators compared to GPUs used for convolutional Neural (CNN) and Deep Neural (DNN) Networks are described. The talk covers memory (volatile and nonvolatile) solutions for CNN/DNN applications at extremely low Vmin. The talk also focuses on in-memory computation. Binary and analog applications using non-volatile memories (NVM) are illustrated. Accelerator architectures for bitwise convolution that features massive parallelism with high energy efficiency are described for both binary and analog memories. In our earlier work, numerical experiment results show that the binary CNN accelerator on a digital ReRAM-crossbar achieves a peak throughput of 792 GOPS at the power consumption of 4.5 mW, which is 1.61 times faster and 296 times more energy-efficient than a high-end GPU. Finally, the talk summarizes challenges and future directions for circuit applications for edge and data-centric accelerators.

Artificial intelligence (AI) studies the theory and development of computing systems able to learn, reason, act and adapt. Integrated circuit (ICs), powered by the semiconductor technology, enable all modern computing systems with an amazing level of integration, e.g., a small chip (<1cm²) nowadays can integrate billions of transistors. As the semiconductor technology enters the era of extreme scaling (1x nm), IC design and manufacturing complexities are extremely high. Intelligent cross-layer design and manufacturing co-optimizations are in critical demand for better performance, power, yield, reliability, security, time-to-market, and so on. This talk will discuss the synergy between modern AI technologies (e.g., deep learning) with intelligent deep-nanoscale IC design and manufacturing. Several case studies will be presented in terms of AI for IC, including advanced lithography modeling, mask synthesis, physical design, and security. Meanwhile, customized ICs for AI can further improve the training and inference performance-energy efficiency by orders of magnitude. Thus, the co-evolution of AI algorithms and IC technologies shall be investigated jointly to enhance the research and development of each other.

Despite tremendous advancement of digital IC CAD tools over the last few decades, analog IC layout is still heavily manual which is very tedious and error-prone. This talk will discuss the overall objective and preliminary results of MAGICAL, a human-intelligence inspired, fully-automated analog IC layout tool sponsored by the DARPA IDEA program. MAGICAL starts from an unannotated netlist, perform automatic layout constraint generation and device generation, then perform automatic placement, legalization, well generation, followed by automatic routing (including signal and power/clock routing) to obtain GDSII, guided by various analytical, heuristic, and machine learning algorithms. MAGICAL has obtained promising initial results. It will be made open source to the public later in 2019. I will also discuss challenges and future directions.

The advancement of photonic integrated circuits (PICs) brings new opportunities for optical computing. Optical computing, as a promising alternative to traditional CMOS computing, has great potentials to offer ultra-high speed and low-power in information processing and communications. This seminar will discuss some recent efforts and results on optical computing on PICs, including optical adder/multiplier designs, optical logic synthesis, and optical neural network. The advantages, limitations, and possible research directions will be discussed.

As Moore’s Law based device scaling and accompanying performance scaling trends are slowing down, there is increasing interest in new technologies and computational models for fast and more energy-efficient information processing. Meanwhile, there is growing evidence that, with respect to traditional Boolean circuits and von Neumann processors, it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Nevertheless, some beyond-CMOS devices demonstrate other unique characteristics such as ambipolarity, negative differential resistance, hysteresis, and oscillatory behavior. Exploiting such unique characteristics, especially in the context of alternative circuit and architectural paradigms, has the potential to offer orders of magnitude improvement in terms of power, performance, and capability.

In order to take full advantage of beyond-CMOS devices, however, it is no longer sufficient to develop algorithms, architectures, and circuits independent of one another. Cross-layer efforts spanning from devices to circuits to architectures to algorithms are indispensable. This talk will examine energy-efficient neural network accelerators for embedded applications in this context. Several deep neural network accelerator designs based on cross-layer efforts spanning from alternative device technologies, circuit styles and architectures will be highlighted. A comprehensive application-level benchmarking study for the MNIST dataset will be presented. The discussions will demonstrate that cross-layer efforts indeed can lead to orders of magnitude gain towards achieving extreme scale energy-efficient processing.

The inevitable slowdown of the CMOS scaling trend has fueled an explosion of research endeavors in finding a CMOS replacement. However, recent studies suggest that many of the emerging devices being investigated, if used as simple drop-in replacement for MOSFETs, may only achieve speedups that mirror historical trends in the best case. The consensus from the community is that cross-layer efforts are essential in combating the CMOS scaling challenge with emerging devices. This talk presents such an effort centered around a particular emerging device, ferroelectric FETs (FeFETs).

An FeFET is made by integrating a ferroelectric material layer in the gate stack of a MOSFET. It is a non- volatile device that can behave as both a transistor and a storage element. This unique property of FeFETs enables area efficient and low-power fine-grained logic-in-memory, which are desirable for many data analytic and machine learning applications. This presentation will elaborate novel circuits based on FeFETs to accomplish basic logic-in-memory operations, ternary content addressable memory (TCAM) as well as FeFET based crossbars for binary Convolutional Neural Networks. Comparisons of these FeFET based circuits with other alternative technologies will be discussed.

Wireless networked control systems (WNCSs) are fundamental to many Internet-of-Things (IoT) applications and must work under real-time constraints in order to ensure timely collection of environmental data and proper delivery of control decisions. The Quality of Service (QoS) offered by a WNCS is thus often measured by how well it satisfies the end-to-end deadlines of the real-time tasks executed in the WNCS. Network resource management in WNCSs plays a critical role in achieving the desired QoS. Unexpected internal and external disturbances that may appear in WNCSs concurrently make resource management inherently challenging. The explosive growth of IoT applications especially in terms of their scale and complexity further exacerbate the level of difficulty in network resource management.

In this talk, I first give a general introduction of WNCSs and the challenges that they present to network resource management. In particular, I will discuss the complications due to external disturbances and the need for dynamic data-link layer scheduling. I then highlight our recent work that aims at tackling this challenge. Our work balances the scheduling effort between a gateway (or access points) and the rest of the nodes in a network. It paves the way towards decentralized network resource management in order to achieve scalability. Experimental implementation on a wireless testbed further validates the applicability of our proposed techniques. I will end the talk outlining our on-going effort in this exciting and growing area of research.

Fast growth of the computation cost associated with training and testing of deep neural networks (DNNs) inspired various acceleration techniques. Reducing topological complexity and simplifying data representation of neural networks are two approaches that popularly adopted in deep learning society: many connections in DNNs can be pruned and the precision of synaptic weights can be reduced, respectively, incurring no or minimal impact on inference accuracy. However, the practical impacts of hardware design are often ignored in these algorithm-level techniques, such as the increase of the random accesses to memory hierarchy and the constraints of memory capacity. On the other side, the limited understanding about the computational needs at algorithm level may lead to unrealistic assumptions during the hardware designs. In this talk, we will discuss this mismatch and show how we can solve it through an interactive design practice across both software and hardware levels.

The goal of this seminar is to give an overview of working mechanisms of several emerging nonvolatile memory technologies, i.e., spintronic memory, phase change memory, resistive memory, and ferroelectric memory, etc., and their applications in next-generation storage and computing systems. The presenter will first introduce electrical properties of these memory technologies that make them unique from the mainstream memory technologies. Next, the presenter will discuss some typical circuit designs targeting the concerned applications, i.e., TCAM, on-chip cache, standalone memory, and storage class memory. The presenter will then illustrate the new requirements of next-generation storage and computing systems and their solutions by leveraging the unique properties of emerging memory technologies, such as fast access time, nonvolatility, high integration density, and good CMOS process compatibility. At the end of this talk, the presenter will list some common circuit design challenges of these emerging memory technologies, e.g., high write cost, asymmetric programming performance at 1 and 0, and the approaches that can alleviate these challenges at circuit design and computer architecture levels.

Although Deep Neural Networks (DNN) are ubiquitously utilized in many applications, it is generally difficult to deploy DNNs on resource-constrained devices, e.g., mobile platforms. In practical use, both testing (inference) phase and sophisticated training (learning) phase are required, calling for efficient testing and training methods with higher accuracy and shorter converging time. In this tutorial, we first introduce DNNs from a historical perspective and then present some representative techniques to reduce the computation cost of DNN, including network pruning, model compression, low precision design etc. In rial, we will show some examples to perform and optimize the training and testing of DNN on distributed mobile systems.

• Introduction to neural networks 

• History, structure, algorithms, and software 

This tutorial will provide attendees a holistic and historical view about technology evolutions of emerging nonvolatile memory in devices, circuit design, and architectural applications. The presenter will first briefly describe the basic physics of several important emerging nonvolatile memory technologies – magnetic memory, resistive memory, phase change memory, and ferroelectric memory, as well as some common device engineering tradeoffs. After that, the presenter will introduce several typical emerging memory cell designs that maximize the advantages of these emerging storage devices, e.g., non-volatility, multi-level cell, and small footprint, and alleviate device drawbacks like high programming current/voltage etc. The focus will be given to the circuit design development following the advance in device engineering in last two decades from a device-circuit co-design perspective. The presenter will then go through the computer architectures that have built their memory hierarchy with the emerging non-volatile memory technologies for various concerns on power, performance, and reliability. Again, some solutions that mitigate the drawbacks of emerging memories and significantly enhance the computing systems’ efficiency and robustness will be discussed in details. Finally, the presenter will give the prospect of new applications of emerging nonvolatile memory technologies in future computing systems like neuromorphic computing etc.

• Device physics and basic working mechanisms 
• Device engineering for various applications 
• Memory cell design tradeoffs between area, power, performance, and reliability 
• Special memory cell designs to overcome the device drawbacks and multi-level cells 
• Memory structures for fast access time and high endurance 
• On-chip memory hierarchy: performance-driven designs 
• Off-chip memory hierarchy: density-driven designs 
• Applications in persistency retaining and neuromorphic computing