Many-core system-on-chip (SoC) architecture and design challenges and opportunities spanning edge devices to cloud computing systems inscaled CMOS process are presented. Key techniques for robust and variation-tolerant logic, embedded memory arrays and on-die interconnectfabrics are discussed. Fine-grain multi-voltage design and power management techniques, featuring integrated voltage regulators for widedynamic voltage-frequency operating range and fl exible platform power control across multi-threaded high-throughput near-threshold voltage(NTV) to single-threaded burst performance modes, are elucidated. Smart variation-aware workload mapping, runtime self-adaptation and errordetection and recovery schemes to mitigate impacts of process-voltage-temperature (PVT) variations and aging, and achieve maximumperformance under stringent thermal and energy constraints, are presented. Latest advances in design and process/package for realization ofmonolithic and heterogeneous 2D/3D-integrated compact, effi cient, low supply noise, fi ne-grain, high-bandwidth and fast-response powerconverters and voltage regulators, essential for implementing intelligent system-level power management and adaptation schemes acrosshardware and software, are also highlighted. Real SoC examples are used to demonstrate leading-edge practical systems.

SoC design challenges and opportunities for smart and secure cyberphysical systems in the world of Internet-of-Things (IoT) are presented,focusing on two distinct areas: (1) how to deliver uncompromising performance and user experience while minimizing energy consumption, and(2) how to provide cryptographic-quality “roots of trust” in silicon and resistance to physical side channel attacks with minimal overhead. SoCdesigns that span a wide range of performance and power across diverse platforms and workloads, and achieve robust near-threshold-voltage(NTV) operation in nanoscale CMOS, are discussed. Techniques to overcome the challenges posed by device parameter variations, supplynoises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations are presented. TrueRandom Number Generator (TRNG) and Physically Unclonable Function (PUF) circuits, the two critical silicon building blocks for generatingdynamic and static entropy for encryption keys and digital fi ngerprints, respectively, are discussed. Power and electromagnetic physical side-channel-attack detection and mitigation techniques for enabling robust hardware security are also presented.

Recently, a lot of effort has been put into developing formal verification approaches by both academic and industrial research. In practice, these techniques often give satisfying results for some types of circuits, while they fail for others. A major challenge in this domain is that the verification techniques suffer from unpredictability in their performance. The only way to overcome this challenge is the calculation of bounds for the space and time complexities. If a verification method has polynomial space and time complexities, scalability can be guaranteed.
In this seminar, we review recent developments in formal verification techniques and give a comprehensive overview of Polynomial Formal Verification (PFV). In PFV, polynomial upper bounds for the run-time and memory needed during the entire verification task hold. Thus, correctness under resource constraints can be ensured. We discuss the importance and advantages of PFV in the design flow. Formal methods on the bit-level and the word-level, and their complexities when used to verify different types of circuits, like adders, multipliers, or ALUs are presented. The current status of this new research field and directions for future work are discussed.

System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of embedded systems. Reusable hardware Intellectual Property (IP) based SoC design has emerged as a pervasive design practice in the industry to dramatically reduce SoC design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of computing platforms. It is crucial to evaluate the integrity and trustworthiness of third-party IPs for designing trustworthy systems. In this talk, I will introduce a wide variety of hardware security vulnerabilities, design-for-security solutions, and possible attacks and countermeasures. I will briefly describe how the complementary abilities of simulation-based validation, formal verification as well as side channel analysis can be effectively utilized for comprehensive SoC security and trust validation.

Quantum technologies offer promising advantages over classical counterparts in a variety of tasks, including faster computation, secure communication, and high-precision sensors. This tutorial will provide a comprehensive overview of both fundamental concepts and recent advances in design automation of quantum computing. This tutorial will consist of three parts. The first part will describe the fundamentals of quantum computing from the perspective of computer scientists and computer engineers. The second part will describe design automation tools and flows to enable robust quantum computing. It will discuss various quantum algorithms as well as automated methods to map these algorithms on quantum computers. Specifically, it will cover specification languages, quantum compilation, control generation, quantum state preparation, quantum error correction, quantum machine learning, quantum measurement, as well as validation of quantum systems. Finally, it will outline the importance of noise modeling and mitigation methods in todayís noisy intermediate scale quantum computers.

This tutorial will provide a comprehensive overview of security attacks as well as detection techniques using explainable AI. Specifically, the tutorial will consist of six parts. The first part will outline a wide variety of software and hardware security threats and vulnerabilities. The second part will cover various machine learning algorithms, including decision tree, random forest, deep neural network, recurrent neural network, unsupervised learning, zero-shot learning, and reinforcement learning. The third part will introduce explainable AI algorithms to interpret machine learning modelsí behaviors in a human-understandable way, using model distillation, Shapley value analysis, and integrated gradients. The fourth part will discuss state-of-the-art attack detection using explainable AI. The fifth part will cover how to enable hardware acceleration of explainable AI models for real-time vulnerability detection. Finally, it will discuss the security threats toward machine learning models (adversarial attack, poisoning attack, and AI Trojan attack), and effective countermeasures to design robust AI models.

The proliferation of "big data" applications poses significant challenges in terms of speed and scalability for traditional computer systems. The increasing performance gap between CPUs and memory, commonly referred to as the "memory wall," greatly impedes the performance of traditional Von Neumann machines. As a result, neuromorphic computing systems have garnered considerable attention. These systems operate by emulating the charging and discharging processes of neurons and synapse potential in a biologically plausible computing paradigm. Electrical impulses or spikes facilitate inter-neuron communication. The unique encoding of information in the spike domain enables asynchronous event-driven computation and communication, potentially resulting in high energy efficiency. In this seminar, I will introduce several typical computing models of neuron and synapses that can be utilized to build spiking neural networks (SNNs). Additionally, selected inference and learning algorithms for SNNs will be discussed, followed by a brief overview of existing hardware and software solutions for implementing neuromorphic computing. I will further present our Error-Modulated Spike-Timing-Dependent Plasticity (EMSTDP) algorithm, which is capable of supervised training of a deep SNN, and its implementation on a neurosynaptic processor. Compelling results that highlight the potential of this innovative computing paradigm will be presented.

The dynamics of the physical world can be captured by multi-channel time-varying analog signals. From sensing to actuation, to interact with the physical world, IoTs and edge devices must have the ability to detect, classify, and generate patterns in multivariate time series with rich temporal and spatial dynamics. However, limited hardware resources and battery capacity pose significant challenges in information representation and processing. Additionally, the constantly changing environment and mission requirements demands the ability for online learning and adaptation. Inspired by the structure and behavior of biological neural systems, spiking neural network (SNN) models and neuromorphic computing hardware incorporate many energy-efficient features of biological systems making them effective for mobile and edge applications. The neuron and synapse states maintained by membrane potentials provide rich temporal dynamics for pattern detection and generation, making the model ideal for in-memory computing. In this talk I will introduce SNNs and neuromorphic computing techniques for multivariate time series processing. Using neurons modeled as a network of infinite impulse response filters, the SNN can either work as a classifier to detect patterns in the input temporal sequences or as a generator to generate desired temporal sequences. The ability to discern temporal patterns allows for very sparse input representation, where information is encoded by the intervals between spike events. When combined with event-driven computing and communication, such temporal coding results in significant energy savings.

As Moore's law is approaching to the end, designing specialized hardware along with the software that maps the applications onto that hardware is a promising solution. The peak performance of the hardware design is important, while the software also plays a critical role in determining the actual performance. The recent progress in computing-in-memory (CiM) using non-volatile memory (NVM) demonstrates its potential as a specialized accelerator to enhance energy efficiency, particularly at the edge. It is expected that the hardware/software (HW/SW) co-design can further optimize NVM based CiMs and improve the overall performance. However, the current process for HW/SW co-design in CiM has not been well addressed. Additionally, it is difficult to design and optimize NVM based CiMs due to the huge design space. Thus, in this talk, we will introduce novel co-exploration frameworks for algorithms, CiM architectures and various device options including FeFET, ReRAM, and MRAM. We will showcase how our flexible co-exploration framework, Eva-CiM, broadens the design freedom and advances the Pareto frontier between hardware efficiency and algorithm performance for better design trade-offs. Furthermore, we will present the unified optimization of HW/SW to minimize the impact of intrinsic reliability issues in CiM.

Approximate computing is an effective approach to enhance circuit performance and energy efficiency by deliberately sacrificing accuracy. Among various arithmetic units, multiplication is a widely used but possibly the most energy-consuming operation. Its approximate variants have received growing interests from both academia and industry. However, the accuracy and energy efficiency of these approximations can vary greatly depending on how and where they are introduced into the design. This talk will first review various approximation techniques for multiplier design, ranging from circuit- to algorithm-level approaches. Then, we will delve into the recent developments in cross-layer approximate multiplier design, which combines circuit-level customization and algorithm-level optimization. Such a cross-layer perspective can address the above concerns by linking the algorithm specification to the circuit details to achieve the desired energy efficiency. We will also present results from RTL implementations in comparison to the prior works, demonstrating that the cross-layer methodology can lead to almost an order of magnitude improvement in energy efficiency with minimal accuracy loss.

Relentless scaling in semiconductors and the growing complexity of System-on-Chip (SoC) integration have presented various challenges in design sign-off, from problem size to formulation complexity. On the other hand, the success of Machine Learning (ML), particularly deep learning, has sparked widespread interest in ML-powered design automation. A notable example is Google's Placer, which uses deep reinforcement learning and has garnered much attention in academia and industry. It's important to note that unlike many computer vision problems, sign-off problems already have a well-established mathematical and physical law-based system. This raises questions about the scope and effectiveness of ML techniques in sign-off Electronic Design Automation (EDA). Moreover, sign-off verification requires high accuracy and, in some cases, exact solutions, while ML techniques are known to result in unpredictable accuracy loss. This talk will start with a comprehensive overview of the directions in which ML will improve the cost and efficiency of sign-off. It will then delve into the successful applications of ML in power and timing sign-off, as well as its deployment in industrial practices to speed up sign-off convergence. Finally, the talk will summarize the lessons we learned during this trip of bringing ML to sign-off problems.

Cyber-physical systems (CPS), such as automotive, manufacturing, and power grid systems, are engineered systems built from and depend upon the seamless integration of computation and physical components. Embedded systems comprising of hardware and software systems are the primary enabling technology for these cyber-physical systems. Moreover, when cyber-physical systems get connected to the Internet, it forms the Internet-of-Things (IoT). Today, CPSs can be found in security-sensitive areas such as aerospace, automotive, energy, healthcare, manufacturing transportation, entertainment, and consumer appliances. Compared to the traditional information processing systems, due to the tight interactions between cyber and physical components in CPSs and closed-loop control from sensing to actuation, new vulnerabilities emerge from the boundaries between various layers and domains. In this seminar, Dr. Al Faruque will discuss how new vulnerabilities emerge at the intersection of multiple components and subsystems and their different hardware, software, and physical layers. Several recent examples from various cyber-physical systems (e.g., an automotive system) will be presented in this talk. To understand these new vulnerabilities, a very different set of methodologies and tools are needed. Defenses against these vulnerabilities also demand new hardware/software co-design approaches. The seminar will highlight recent developments in this regard. This seminar's primary goal will be to highlight various research challenges and the need for novel scientific solutions from the EDA research community and definitely from the larger embedded systems, cyber-physical systems, distributed computing systems, and computer architecture research communities.

Over the years, design automation methodologies have been employed to alleviate the extensive task of manual system design across the different levels of abstraction, as in the EDA, Embedded, and Cyber-Physical Systems (CPS) domains. As Deep Learning (DL) becomes the enabling technology of today's intelligent applications, design automation methodologies have found their way into the DL field through techniques like Neural Architecture Search (NAS). Such methods are providing high-performing neural architecture models compared to the manually designed ones. Yet, driven by the application requirements of real-time inference and computation efficiency, the current design tendency is to push the computation to the edge of the network itself, be it on the user's end devices or the network gateways. Consequently, device specifications, application characteristics, and computing paradigms must be integrated within the design automation methodologies. Therefore, sophisticated techniques are needed to capture the interacting dynamics of the different system components in terms of compute capabilities, resource utilization, and intra-system communication. In this seminar, Dr. Al Faruque will discuss how to implement design automation methodologies for DL applications, tuned to the different requirements of modern smart edge-AI systems. He will present several examples ranging from low-power wearable devices to compute-intensive Autonomous Vehicles. Moreover, this seminar will highlight how the emerging split computation and early-exit computing can be incorporated into the design optimization aspect to provide AI-enabled edge systems for different applications.

Embedded systems comprising hardware and software systems are the primary enabling technology for modern cyber-physical systems such as home devices, autonomous vehicles, and industrial manufacturing machines. The global embedded system market is estimated to grow from 86 billion dollars to 116 billion dollars by 2025. This phenomenon also reveals that these systems can now or in the future generate a considerable amount of data, so making good use of these data has become very important in this field. Conventional machine learning only applies to the data in the Euclidean form, while in practice, more and more data appears as non-Euclidean data such as graphs, manifolds, etc. To use these ML models, researchers have to manually engineer features from these non-Euclidean data with their expertise in the field and spend efforts in tuning them to avoid the loss of information from original data. In this case, Graph Learning techniques have become increasingly important as they can bypass this step and directly process the graph data. In this seminar, Dr. Al Faruque will discuss how to apply graph learning techniques to different applications for embedded systems. This talk will mainly present the approaches leveraging graph learning for Autonomous Driving Systems (ADSs), hardware security, and software security. In ADSs, recent work by Dr. Al Faruque leverages scene-graph as an intermediate representation to better understand the driving scenes and infer the level of riskiness for actions. In hardware security, Dr. Al Faruque’s group utilizes graph representations of hardware designs, such as abstract syntax trees (ASTs) or control-flow graphs (CFGs), and graph learning approaches to solve hardware security problems (hardware trojan detection/IP piracy detection) at the behavioral level.

The steady rise of intelligence and autonomy over a scale of distributed, connected and smart components is heralding the era of Internet-of-Intelligence. Without adequate safeguards in place, such components can lead to terrible consequences. In this talk, I will discuss three topics - namely, vulnerability, design for security and privacy of such edge–computing scenarios. The vulnerability aspect will be demonstrated through multiple attacks that we conducted, using practical case studies on edge devices. The design for security perspective will be discussed, first, through system-level security-by-design methodologies; second, through efficient lightweight cryptographic accelerator designs and design automation flows; third, through automation of attack/prevention techniques. Finally, the privacy perspective will be presented through an innovative tunable compression technique, realized on top of a video/image-processing platform.

The continued scaling of horizontal and vertical physical features of silicon-based complementary metal-oxide-semiconductor (CMOS) transistors, termed as “More Moore”, has a limited runway and would eventually be replaced with “Beyond CMOS” technologies. There has been a tremendous effort to follow Moore’s law but it is currently approaching atomistic and quantum mechanical physics boundaries. This has led to active research in other non-CMOS technologies such as memristive devices, carbon nanotube field-effect transistors, quantum computing, etc. Several of these technologies have been realized on practical devices with promising gains in yield, integration density, runtime performance, and energy efficiency. Their eventual adoption is largely reliant on the continued research of Electronic Design Automation (EDA) tools catering to these specific technologies. Indeed, some of these technologies present new challenges to the EDA research community, which are being addressed through a series of innovative tools and techniques. In this tutorial, we will particularly cover the two phases of EDA flow, logic synthesis, and technology mapping, for two types of emerging technologies, namely, in-memory computing and quantum computing.

The rise of AI and in particular, deep learning (DL), is a key driver for innovations in computing systems. There is a significant effort towards the design of custom accelerator chips based on reduced precision arithmetic and highly optimized data flow. However, the need to shuttle millions of synaptic weight values between the memory and processing units remains unaddressed. In-memory computing (IMC) is an emerging computing paradigm that addresses this challenge of processor-memory dichotomy. Attributes such as synaptic efficacy and plasticity can be implemented in place by exploiting the physical attributes of memory devices such as phase-change memory (PCM). In this talk, I will give a status update on where in-memory computing stands with respect to DL acceleration. I will present some recent algorithmic advances for performing accurate DL inference and training with imprecise IMC. I will also present state-of-the-art IMC compute cores based on PCM fabricated in 14nm CMOS technology and touch upon some systems-level aspects. Finally, I will present some applications of IMC that transcend conventional DL such as memory-augmented neural networks and spiking neural networks.

Traditional computing systems involve separate processing and memory units. However, data movement is costly in terms of time and energy and this problem is aggravated by the recent explosive growth in highly data-centric applications related to artificial intelligence. This calls for a radical departure from the traditional systems and one such computational approach is in-memory computing. Hereby certain computational tasks are performed in place in the memory itself by exploiting the physical attributes of the memory devices. In this lecture, I will give an overview of the primary charge-based and resistance-based Seminar Titles (Maximum 3) memory devices being explored for in-memory computing as well as the key computational primitives they enable. Subsequently, I will present an overview of the key applications of in-memory computing that span scientific computing, signal processing, optimization, machine learning, deep learning, and stochastic computing.

In the past a few years, powered by the strong need of edge intelligence, there has been an increasing interest in deploying deep neural networks on tiny hardware with limited computing power and energy (tinyML). A fundamental question needs to be addressed: given a specific edge intelligence task, what is the optimal neural architecture and the tailor-made hardware in terms of accuracy and efficiency? Earlier approaches attempted to address this question through hardware-aware neural architecture search (NAS), where fa fixed hardware design such as microcontrollers or light-weight CPUs are taken into consideration when designing neural architectures. However, we believe that the most powerful and elegant solutions should come from hardware that allows customization, such as FPGAs, ASICs, or Computing-in-Memory accelerators. For these platforms, we are the first to establish the concept of software/hardware co-design, which simultaneously explore neural architecture and the hardware design to identify the best pairs that maximize both test accuracy and hardware efficiency. In this talk, we will present the novel co-exploration frameworks for neural architecture and various hardware platforms including FPGA, ASIC and Computing-in-Memory, all of which are the first in the literature. We will demonstrate that our co-exploration concept greatly opens up the design freedom and pushes forward the Pareto frontier between hardware efficiency and test accuracy for better design tradeoffs in tinyML.

Despite the pursuit of quantum advantages in various applications, the power of quantum computers in executing neural network has mostly remained unknown, primarily due to a missing tool that effectively designs a neural network suitable for quantum circuit. In this talk, I will present our open-source neural network and quantum circuit co-design framework, namely QuantumFlow, to address the issue. In QuantumFlow, we represent data as unitary matrices to exploit quantum power by encoding n = 2k inputs into k qubits and representing data as random variables to seamlessly connect layers without measurement. Coupled with a novel algorithm, the cost complexity of the unitary matrices-based neural computation can be reduced from O(n) in classical computing to O(polylog(n)) in quantum computing. I will further demonstrate the results on MNIST dataset using IBM quantum processors, which show that QuantumFlow can achieve an accuracy of 94.09% with a cost reduction of 10.85 × against the classical computer. This is the first time that quantum advantage is demonstrated practically on the inference of deep neural networks, and the tool has been accessed over 1,200 times within its first month of release.

With the prevalence of deep neural networks, machine intelligence has recently demonstrated performance comparable with, and in some cases superior to, that of human experts in medical imaging and computer assisted intervention. Such accomplishments can be largely credited to the ever-increasing computing power, as well as a growing abundance of medical data. As larger clusters of faster computing nodes become available at lower cost and in smaller form factors, more data can be used to train deeper neural networks with more layers and neurons, which usually translate to higher performance and at the same time higher computational complexity. For example, the widely used 3D U-Net for medical image segmentation has more than 16 million parameters and needs about 4.7×1013 floating point operations to process a 512×512×200 3D image. The large sizes and high computation complexity of neural networks have brought about various issues that need to be addressed by the joint efforts between hardware designers and medical practitioners towards hardware aware learning. In this talk, I will present novel solutions for the data acquisition and data processing stages in medical image computing respectively, using hardware-oriented schemes for lower latency, memory footprint and higher performance in embedded platforms. I will discuss how our hardware-aware machine learning approaches led to the realtime MRI segmentation for prosthetic valve implantation assistance, and enabled the world’s first AI assisted telementoring of cardiac surgery on April 3, 2019.

Recently machine learning, especially deep learning is gaining much attention due to the breakthrough performance in various cognitive tasks. Machine learning for electronic design automation is also gaining traction as it provides new techniques for many of the challenging design automation problems with complex nature. Thermal and power modeling and online regulation for many-core and embedded systems have been intensively studied in the past. But real-time full-chip thermal estimation for commercial multi-core processors is still a challenging problem. In this talk, I will first show that one can build an accurate transient thermal map of commercial off-the-shelf multi-core microprocessors based on the given on-chip sensors and real-time utilization information based on a data-driven deep learning-based approach. The new models are directly based on the available real-time high-level chip utilization and thermal sensor information of commercial chips without any assumption of additional physical sensors requirements. I will explore different deep learning neural networks (DNN) architectures such as recurrent neural networks and generative adversarial networks and show how to frame the full-chip thermal map learning problems as the supervised data-driven learning processes for those DNN networks for commercial many-core processors. Our work is further enabled by an infrared thermography system, which can provide lucid thermal maps of commercial multi-core CPUs and many-core GPUs while nominal working conditions are maintained on the chip. 

As machine learning, especially deep learning, has been proved to be effective for capturing spatial and temporal dynamics behaviors, it brings new opportunities for addressing those difficult tasks. In this talk, I will look at the emerging machine learning/deep learning-based approaches for the VLSI interconnect reliability modeling, optimization, and dynamic management. I first present a machine learning-based approach to model hydrostatic stress in the multi-segment interconnects based on the generative adversarial learning, in which we treat the stress modeling as a time-varying 2D image-to-image conversion problem and the resulting solution provide an order of magnitudes over existing numerical method and 10x over state of art semi-analytic method. Second, based on the observation that VLSI multi-segment interconnects trees can be naturally viewed as graphs. I will present a new graph convolution network (GCN) model, called EMgraph, to consider both node and edge embedding features, to estimate the transient EM stress of interconnecting trees. The new method can lead 10X speedup over GAN-based EM analysis with transferable knowledge to predict stress on new interconnect trees. To mitigate the long-term aging effects due to NBTI, EM, and HCI, I further present an accuracy reconfigurable stochastic computing (ARSC) framework for dynamic reliability and power management. Different than the existing stochastic computing works, where the accuracy versus power/energy trade-off is carried out in the design time, the new ARSC design can change the accuracy or bit-width of the data in the run-time so that it can accommodate the long-term aging effects by slowing the system clock frequency at the cost of accuracy while maintaining the throughput of the computing.

Electromigration (EM) remains the top killer for the copper-based interconnects in current and near-future advanced VLSI technologies. As the technologies scale, the allowable current density continues to decrease due to EM while the required current density to drive the gates increases. 2015 ITRS predicts that EM lifetime of interconnects of VLSI chips will be reduced by half for each generation of technology nodes. The most important observation from our recent study is that EM analysis needs to consider multi-wire segments in the same metal layer to be more accurate and less conservative for all the advanced deep micro techniques. Existing current density-based EM check can lead to significant over-design and loss of design optimization opportunities. Our lab’s recent mission is to change this widely adopted industry design practice to move into new generation EM modeling, assessment, and design techniques. In this talk, I will present recent research works in my research lab (VSCLAB) at UC Riverside. I will cover newly proposed physics-based electromigration (EM) models, especially the physics-based three-phase EM models and full-chip EM-induced IR drop analysis techniques. I will first present the recently proposed three-phase EM model, which much more accurately describes the EM failure process and post-voiding resistance change phenomena. I then introduce two new EM immortality check methods for general multi-segment interconnect wires, which can be viewed as the Blech Product to multi-branch interconnects. Then I will present a novel fast finite difference method (FDM) for EM stress analysis based on frequency domain model order reduction techniques. On top of this, I will present the recently proposed coupled EM-IR drop analysis tool, EMspice, for full-chip EM-induced IR drop analysis of power delivery networks and show how it integrates with Synopsys ICC design flow. EMspice incorporates the latest EM modeling and analysis techniques for multi-segment interconnects, such as EM immortality checks considering both nucleation and incubation phases, the interaction between IR drop, and EM aging effects in the post-void EM phase, EM recovery effects and temporal temperature effects etc. Last, not least, I will present recent work on EM-aware power grid design and optimization, which exploits the recently developed EM modeling and assessment techniques for multi-segment interconnect wires.

Recently machine learning, especially deep learning is gaining much attention due to the breakthrough performance in various cognitive applications. Machine learning for electronic design automation (EDA) is also gaining significant Tutorial Titles (Maximum 3) traction as it provides new computing and optimization paradigms for many challenging design automation problems with complex nature. Today’s chip designers and EDA developers face several many challenges in advanced technologies from technology and physical levels to the circuit and multi-core chip levels. Given the complex nature of both modeling and online thermal/power/reliability control challenges in advanced technologies from one hand, there are a lot of potentials in using the latest advances in machine learning to tackle those hard problems towards developing intelligent runtime management schemes. In this tutorial, I present several novel machine-learning-based solutions to the after-mentioned EDA challenges. I will first focus on novel full-chip thermal and power map estimation techniques using the recurrent neural networks (RNN) and generative adversarial (GAN) network methods for commercial multi-core processors first. I will show for the first time the new capability of real-time full-chip thermal tracking for commercial microprocessors. I also show how to obtain accurate power density maps and thermal maps for those commercial chips with practical heat sinks for more advanced thermal/power/reliability management. I also present the recent proposed ThermGAN approach, which uses the adverbial generative learning method to estimate the full-chip thermal maps and compared favorably to the existing RNN based methods. For dynamic thermal/reliability management, I will present a recently proposed deep reinforced learning (DRL) based control method based on the reliability of workload-dependent true hotspot identification and modeling of commercial multi-core processors. For electromigration (EM) induced VLSI to interconnect reliability modeling and optimization, I will present the recently proposed EMGraph approach, which applied graph convolutional networks (GCN) to consider both node and edge embedding features, to estimate the transient EM stress of multi-segment interconnect trees.

In this tutorial, I will present some of the recent research works in my research lab (VSCLAB) at UC Riverside. First, I will review a recently proposed physics-based three-phase EM model for multi-segment interconnect wires, which consists of nucleation, incubation, and growth phases to completely model the EM failure processes in typical copper damascene interconnects. The new EM model can predict more accurate EM failure behaviors for multi-segment wires such as interconnects with reservoir and sink segments. Second, I will present newly proposed fast aging acceleration techniques for efficient EM failure detections and validation of practical VLSI chips. I will present the novel configurable reservoir/sink-structured interconnect designs in which the current in the sink segment can be activated/deactivated dynamically during operation. In this way, the stress conditions of the interconnect wires can be increased and the lifetime of the wires can be reduced significantly. Afterward, I will present the compact dynamic EM models for general multi-segment interconnect wires and voltage-based EM immortality check algorithm for general interconnect trees. Then I will present a fast 2D stress numerical analysis technique based on the Krylov subspace and finite difference time domain methods (FDTD) for general interconnect wire’s structure. The proposed numerical analysis method can lead to 100X speedup over the simple FDTD method and can be applied to any interconnect structures for all the EM wear-out phases. Then I will focus on the system-level dynamic reliability management (DRM) techniques based on the newly proposed physics-based EM models. I will show several recent works of the EM-aware DRM for lifetime optimizations for dark-silicon, embedder/real-time systems, and 3D ICs to improve the TSV reliability. Last, not least, I will present the work to consider special temperature gradient impacts on EM due to the Joule heating effect. The spatial temperature gradient induced metal atom migration effects, also called temperature migration (TM), was shown to be as significant as the EM itself as technology advances. In our work, I will show how to consider TM effects in both existing EM immortality check and semi-analytic based approaches for the first time.

Long-term reliabilities such as electromigration (EM) induced failures in integrated circuits are expected to grow rapidly with shrinking feature sizes in new technology nodes and novel solutions to address reliability at different levels. This talk presents a new power grid network design and optimization technique that considers the new EM immortality constraint due to EM void saturation volume for multi-segment interconnects. When a void is formed, it is considered to be a failure in traditional EM models. However, this is quite a conservative assumption as a void may never grow to sufficient volume to make a significant change to the wire resistance. By considering saturation volume for multisegment interconnects wires, we can remove such conservativeness in the EMaware on-chip power grid design. Along with another new proposed immortality constraint for the EM nucleation phase for multi-segment wires, I will show that both EM immortality constraints can be naturally integrated into the existing programming-based power grid optimization framework. To mitigate the overly conservative nature of the optimization formulation, I will further explore two strategies: first, we size up failed wires to meet one of the immortality conditions subject to design rules; second, I will consider the EM-induced aging effects on power supply networks for a target lifetime, which allows some short-lifetime wires to fail and optimizes the rest of the wires. Last, not least, I will present our recent work using deep neural networks to model the full-chip EM-induced IR drop and leveraging of the differential feature of DNN for fast sensibility calculation for sensitivity-guided full-chip EM-aware power grid optimization.