Webinar CAD For Assurance: Panel 2 Side-channel leakage - Can CAD come to the rescue? Patrick Schaumont , Serge Leef , Jasper van Woudenberg , Colin O’Flynn , Francesco Regazzoni CAD For Assurance: Panel 2 Side-channel leakage - Can CAD come to the rescue? × More information provided here.
Webinar CAD For Assurance: Side-Channel Analysis and MIMI Debdeep Mukhopadhyay , Jonathan Cruz , Sayandeep Saha , Patanjali SLPSK CAD For Assurance: Side-Channel Analysis and MIMI × Abstract Side-Channel Analysis - Debdeep Mukhopadhyay (IIT Kharagpur) 30-min demo with a 10-min Q&A CAD Tool: https://cadforassurance.org/tools/sca/exp-fault/ MIMI - Patanjali SLPSK and Jonathan Cruz (UF) 30-min demo with a 10-min Q&A CAD Tool: https://cadforassurance.org/tools/ic-trust-verification/mimi/ The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner, with an easy-to-search and easy-to-access interface. We’re including information on many major CAD tools the research community has developed over the past decade, including open-source license-free or ready-for-licensing tools, associated metrics, relevant publications, and video-demos. We are also delighted to announce that a series of virtual CAD for Assurance tool training webinars starting in February 2021. Additional information on these webinars is available at the CAD for Assurance website at https://cadforassurance.org/.
Webinar CAD For Assurance: NEOS Toolset and Deep Learning-Based Model Building Attacks on Arbiter PUF Compositions Kaveh Shamsi , Rajat Subhra Chakraborty , Pranesh Santikellur CAD For Assurance: NEOS Toolset and Deep Learning-Based Model Building Attacks on Arbiter PUF Compositions × Abstract NEOS Toolset by Kaveh Shamsi (UT-Dallas) and Deep Learning-Based Model Building Attacks on Arbiter PUF Compositions by Rajat Subhra Chakraborty (IIT Kharagpur) and Pranesh Santikellur (IIT Kharagpur). The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner, with an easy-to-search and easy-to-access interface. We’re including information on many major CAD tools the research community has developed over the past decade, including open-source license-free or ready-for-licensing tools, associated metrics, relevant publications, and video-demos. We are also delighted to announce that a series of virtual CAD for Assurance tool training webinars starting in February 2021. Additional information on these webinars is available at the CAD for Assurance website at https://cadforassurance.org/.
Webinar CAD For Assurance: RTL Logic Attacks and SMT Attack Chandan Karfa , Avesta Sasan CAD For Assurance: RTL Logic Attacks and SMT Attack × Abstract The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner, with an easy-to-search and easy-to-access interface. We’re including information on many major CAD tools the research community has developed over the past decade, including open-source license-free or ready-for-licensing tools, associated metrics, relevant publications, and video-demos. We are also delighted to announce that a series of virtual CAD for Assurance tool training webinars starting in February 2021. Additional information on these webinars is available at the CAD for Assurance website at https://cadforassurance.org/.
Webinar CAD for Assurance: NETA Toolset and FEDS, SAFARI, XFC Dr. Travis Meade , Jim Geist , Chester Rebeiro CAD for Assurance: NETA Toolset and FEDS, SAFARI, XFC × Abstract CAD for Assurance tool training virtual webinars Part 1: NETA Toolset with Dr. Travis Meade and Jim Geist (University of Central Florida) Part 2: FEDS, SAFARI, XFC with Chester Rebeiro (Indian Institute of Technolgy Madras)
Webinar Closing the Virtuous Cycle of AI for IC and IC for AI David Pan Closing the Virtuous Cycle of AI for IC and IC for AI × Abstract The recent artificial intelligence (AI) boom has been primarily driven by three confluence forces: algorithms, data, and computing power enabled by modern integrated circuits (ICs), including specialized AI accelerators. This talk will present a closed-loop perspective for synergistic AI and agile IC design with two main themes, AI for IC and IC for AI. As semiconductor technology enters the era of extreme scaling, IC design and manufacturing complexities become extremely high. More intelligent and agile IC design technologies are needed than ever to optimize performance, power, manufacturability, design cost, etc., and deliver equivalent scaling to Moore’s Law. This talk will present some recent results leveraging modern AI and machine learning advancement with domain-specific customizations for agile IC design and manufacturing closure. Meanwhile, customized ICs, including those with beyond-CMOS technologies, can drastically improve AI performance and energy efficiency by orders of magnitude. I will present some recent results on hardware/software co-design for high-performance and energy-efficient optical neural networks. Closing the virtuous cycle between AI and IC holds great potential to advance the state-of-the-art of each other significantly.
Webinar An EDA Researcher’s Journey Into AI Yiran Chen An EDA Researcher’s Journey Into AI × Abstract Artificial Intelligence (A) ubiquitously impacts almost all research societies including electronic design automation (EDA). Many scholars with mathematic and modeling backgrounds have shifted their focuses onto applying AI technologies to their research or directly working on AI problems. As a researcher with a Ph.D. training of EDA and circuit designs, I started my AI-relevant research since late 2000s, i.e., neuromorphic computing that implements hardware to accelerate computation of biologically plausible learning models. In this talk, I will review the development process of my research from neuromorphic computing to a broader scope of AI, including machine learning accelerator designs, neural network quantization and pruning, neural architectural search, federated learning, and neural network robustness, privacy, security, etc., and how I benefit from my EDA background.
Distinguished Lecturer Distributed Visual Analytics Vijaykrishnan Narayanan Distributed Visual Analytics × Abstract Visual content continues to be on the rise. Increasingly, visual analytics are part of computational pipelines supporting latency-sensitive and interactive applications such as situational awareness, which combine content dynamically aggregated from sensors and end-user devices. The talk will highlight assistive visual systems for persons with visual impairments and a pollinator-tracking system as examples of such end uses. Using these application contexts, the design space of these distributed sensors will be explored with focus on communication costs. Next, the talk will focus on Video query processing that is evolving from applications that query pre-extracted metadata using traditional query processing techniques to applications that directly analyze geometry, semantics, and content in the video bitstream. This talk will showcase ongoing efforts in system level design. Finally, we will show some new opportunities with the shift from 2D to 3D sensors. The talk leverages effort from collaborators from the SRC JUMP Visual Analytics team and the NSF Expeditions in Computing Visual Cortex on Silicon program.
Webinar DAWN: Quantum Computing & Design Automation Challenges & Opportunities Oliver Dial , Ross Duncan , Carmen G. Almudever , Robert Wille We are excited to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote and individual speaker webinars, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. DAWN: Quantum Computing & Design Automation Challenges & Opportunities × More information provided here.
Webinar DAWN: Publishing in EDA Transactions, Journals, and Magazines Rajesh K. Gupta , X. Sharon Hu , Tulika Mitra , Ramesh Karri , Jörg Henkel , We are excited to announce Design Automation WebiNar (DAWN) to drive research momentum and ensure our community remains at the cutting edge. Different from conventional keynote and individual speaker webinars, DAWN is a special-session-style webinar. DAWN is formed by multiple presentations on focused topics by leading experts in our community. The fourth event in this series is a panel on the topic "Publishing in EDA Transactions, Journals, and Magazines". DAWN: Publishing in EDA Transactions, Journals, and Magazines × More information provided here.
Webinar DAWN: Secure Silicon Recent Developments and Upcoming Challenges Mark M. Tehranipoor , Gang Qu , Brandon Wang , Ahmad-Reza Sadeghi Talk 1 (0‘-25‘): Keys to Hardware Security Talk 2 (25‘-50‘): Automated Implementation of Secure Silicon Talk 3 (50‘-75‘): Assessment of Hardware Security and Trust Talk 4 (75‘-100‘): Enclave Computing on RISC-V: A Brighter Future for Platform Security? DAWN: Secure Silicon Recent Developments and Upcoming Challenges × More information provided here.
Webinar DAWN: Career Development for Scholars in EDA Research Diana Marculescu , Kwang-Ting Tim Cheng , Giovanni De Micheli , Ayse Coskun , Phillip Stanley-Marbell , Jeyavijayan Rajendran The second Design Automation WebiNar (DAWN) on Career Development for Scholars in EDA Research will be held Tuesday, June 23rd from 9:00-10:30 am CDT / 10-11:30 pm HKT / 4-5:30 pm CEST. DAWN: Career Development for Scholars in EDA Research × Abstract The second Design Automation WebiNar (DAWN) on Career Development for Scholars in EDA Research will be held Tuesday, June 23rd from 9:00-10:30 am CDT / 10-11:30 pm HKT / 4-5:30 pm CEST.
Webinar DAWN: Machine Learning for EDA Azalia Mirhoseini , Anna Goldie , David Pan , Jiang Hu , Song Han , Shao-Yun Fang Talk 1 (0‘-20‘): Reinforcement Learning for Placement Optimization Talk 2 (20‘-35‘): AI-Enabled Agile IC Physical Design and Manufacturing Talk 3 (35‘-50‘): Plug-in Use of Machine Learning and Beyond Talk 4 (50‘-65‘): Efficient AI, TinyML, Model Compression Talk 5 (65‘-80‘): Pin Access Optimization Using Machine Learning Panel (80‘-120‘) Q&A DAWN: Machine Learning for EDA × More information provided here.
Conference Special Session New Directions in Distributed Deep Learning: Bringing the Network at Forefront of IoT Design Radu Marculescu New Directions in Distributed Deep Learning: Bringing the Network at Forefront of IoT Design × More information provided here.
Conference Special Session Building E2E IoT Applications with QoS Guarantees Selma Saidi Building E2E IoT Applications with QoS Guarantees × More information provided here.
Conference Special Session In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview Kaushik Ravindran In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview × More information provided here.
Conference Special Session Machine Learning Based Sice Channel Attacks and Countermeasures Marilyn Wolf Machine Learning Based Sice Channel Attacks and Countermeasures × More information provided here.
Conference Special Session Autonomous Warehouse-Scale Computers Parthasarathy Ranganathan Autonomous Warehouse-Scale Computers × More information provided here.
Conference Special Session Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs Jürgen Teich Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs × More information provided here.
Conference Special Session Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs Michael Kishinevsky Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs × More information provided here.
Conference Special Session Efficient Synthesis of Compact Deep Neural Networks Niraj K. Jha Efficient Synthesis of Compact Deep Neural Networks × More information provided here.
Conference Special Session Creating an Agile Hardware Design Flow Priyanka Raina Creating an Agile Hardware Design Flow × More information provided here.
Conference Special Session Chipyard - Integrated SoC Design, Simulation, Implementation Environment Krste Asanović Chipyard - Integrated SoC Design, Simulation, Implementation Environment × More information provided here.
Conference Special Session Developing Privacy-Preserving AI Systems: The Lessons Learned Rosario Cammarota Developing Privacy-Preserving AI Systems: The Lessons Learned × More information provided here.
Conference Special Session Computational Methods for Biological Exploration Louis Scheffer Computational Methods for Biological Exploration × More information provided here.
Video Lecture Current Progress in Quantum Computing Paul Nation Current Progress in Quantum Computing × More information provided here.
Distinguished Speaker/Keynote Simulation Technologies for Image Systems Engineering Brian Wandell Simulation Technologies for Image Systems Engineering × More information provided here.
Distinguished Speaker/Keynote Energy Efficient Neuromorphic Learning And Inference At Nanoscale Gert Cauwenberghs Advances in machine learning and system-on-chip integration have led to the development of massively parallel silicon learning machines with pervasive real-time adaptive intelligence at the nanoscale that begin to approach the efficacy and resilience of biological neural systems... Energy Efficient Neuromorphic Learning And Inference At Nanoscale × Abstract Learning and adaptation are key to natural and artificial intelligence in complex and variable environments. Neural computation and communication in the brain are partitioned into the grey matter of dense local synaptic connectivity in tightly knit neuronal networks, and the white matter of sparse long-range connectivity over axonal fiber bundles across distant brain regions. This exquisite distributed multiscale organization provides inspiration to the design of scalable neuromorphic systems for deep learning and inference, with hierarchical address event-routing of neural spike events and multiscale synaptic connectivity and plasticity, and their efficient implementation in silicon low-power mixed-signal very-large-scale-integrated circuits. Advances in machine learning and system-on-chip integration have led to the development of massively parallel silicon learning machines with pervasive real-time adaptive intelligence at nanoscale that begin to approach the efficacy and resilience of biological neural systems, and already exceed the nominal energy efficiency of synaptic transmission in the mammalian brain. I will highlight examples of neuromorphic learning systems-on-chips with applications in template-based pattern recognition, vision processing, and human-computer interfaces, and outline emerging scientific directions and engineering challenges in their large-scale deployment.
Distinguished Speaker/Keynote Analyzing the Disruptive Impact of a Silicon Compiler Andreas Olofsson As part of the $1.5B Electronics Resurgence Initiative (ERI), DARPA is building the world's first general purpose silicon compilers. Analyzing the Disruptive Impact of a Silicon Compiler × Abstract Recent years have seen an explosion in the cost and time required to design advanced System-on-Chips (SoCs), systems-in-packages (SiPs), and PCBs. As part of the $1.5B Electronics Resurgence Initiative (ERI), DARPA is building the world's first general purpose silicon compilers. The effort involves two distinct research programs, the Intelligent Design of Electronic Assets (IDEA) program aiming to create a no-human-in-the-loop layout generator for digital and analog circuits, and the Posh Open Source Hardware (POSH) program aiming to create a high quality trustable open source ecosystem. Together the efforts will create a universal hardware compiler capable of automatically generating production ready GDSII drawings directly from a rich catalog of trustable source code and schematics for digital as well as analog circuits. Achieving this ambitious goal will require advancing the state of the art in machine learning, optimization algorithms, expert systems, and verification technology. This talk will discuss technical challenges associated with building a universal hardware compiler and provide analysis of potential economic and societal impacts.
Distinguished Speaker/Keynote Emotion Technology, Wearables, and Surprises Rosalind Picard Emotion Technology, Wearables, and Surprises × More information provided here.
Distinguished Speaker/Keynote Accelerating the IoT Tyson Tuttle Accelerating the IoT × More information provided here.
Distinguished Speaker/Keynote The Age of Digital Transformation Chuck Grindstaff The Age of Digital Transformation × More information provided here.
Distinguished Speaker/Keynote IoT: Tales From the Front Line Joe Costello IoT: Tales From the Front Line × More information provided here.
Distinguished Speaker/Keynote Engineering to Medicine Metamorphosis Sani Nassif Engineering to Medicine Metamorphosis × More information provided here.
Distinguished Speaker/Keynote IEEE CEDA Distinguished Speaker Luncheon Mary Jane Irwin IEEE CEDA Distinguished Speaker Luncheon × More information provided here.
Distinguished Speaker/Keynote Socially Acceptable AI-based City Driving Maarten Sierhuis Socially Acceptable AI-based City Driving × More information provided here.
Distinguished Speaker/Keynote The Future of Energy-Efficient Computing Stephen W. Keckler The Future of Energy-Efficient Computing × More information provided here.
Distinguished Speaker/Keynote Back to the Future – Internet of Everything David Culler Back to the Future – Internet of Everything × More information provided here.
Distinguished Speaker/Keynote Disruptive Engineering and Societal Impact Steve Eglash Disruptive Engineering and Societal Impact × More information provided here.
Distinguished Speaker/Keynote Teaching EDA at Planetary Scale: Reflections on the First EDA MOOOCs Rob A. Rutenbar Teaching EDA at Planetary Scale: Reflections on the First EDA MOOOCs × More information provided here.
